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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 14:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers Kyehei Seino, Shigeru Yamashita (Ritsumeikan University)  VLD2022-94 HWS2022-65 |
It is natural to assume that we can perform quantum operations be- tween only two adjacent physical qubits (quantum bit... [more] |
VLD2022-94 HWS2022-65 p.112 |
| HWS, VLD [detail] | 2021-03-04 13:25 |
Online | Online | A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58 |
In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The lat... [more] | VLD2020-83 HWS2020-58 pp.85-90 |
| SWIM, SC | 2018-08-24 10:45 |
Tokyo | Housei Univ. | Trial evaluation on workflow functionality based on Innovation Architecture Shinji Kikuchi (UoA) SWIM2018-7 SC2018-14 |
This paper presents the outline of a tentative conclusion of a thought experiment in analyzing workflow functionality. I... [more] | SWIM2018-7 SC2018-14 pp.1-7 |
| MSS, SS | 2017-01-26 13:30 |
Kyoto | Kyoto Institute of Technology | A Study on Realizability of Choreography Given by Two Communication Diagrams
-- A Study on a Case where Conflicts Exist Between Scenarios -- Toshiki Kinoshita, Toshiyuki Miyamoto (Osaka Univ.) MSS2016-61 SS2016-40 |
For a service-oriented architecture based system, the problem of synthesizing a concrete model, i.e., behavioral model, ... [more] | MSS2016-61 SS2016-40 pp.25-30 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 13:25 |
Kanagawa | Hiyoshi Campus, Keio University | A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87 |
Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] | VLD2015-105 CPSY2015-137 RECONF2015-87 pp.209-214 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 15:10 |
Hokkaido | Hokkaido University | A distributed asynchronous arbiter for ring segmented bus type GALS systems Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] | CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 pp.237-242 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 09:45 |
Kagoshima | An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-79 DC2013-45 |
With process technology scaling, decreasing reliability caused by soft errors as well as increasing the average intercon... [more] | VLD2013-79 DC2013-45 pp.129-134 |
|
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-61 DC2012-27 |
With process technology scaling, heat problems in IC chips as well as increasing the average interconnection delays are ... [more] | VLD2012-61 DC2012-27 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An FPGA Implementation of Reconfigurable Real-Time Vision Architecture Jorge Hiraiwa, Hideharu Amano (Keio Univ.) CPSY2012-54 |
A video processing architecture based on FPGA for real-time embedded vision systems is proposed in this paper. Recently,... [more] | CPSY2012-54 pp.39-44 |
| SIS, IPSJ-AVM | 2012-09-20 10:40 |
Osaka | Tottori Pref. Osaka Office | A High-Performance Multiplierless Hardware Architecture of the Transform Applied to H.265/HEVC Emerging Video Coding Standard Wenjun Zhao, Takao Onoye (Osaka Univ.) SIS2012-18 |
This paper presents a hardware architecture of the transform applied in the emerging video coding standard-HEVC (High Ef... [more] | SIS2012-18 pp.11-16 |
| CAS | 2012-01-19 11:15 |
Fukuoka | Kyushu Univ. | [Invited Talk]
Design Methodology of Group Signature Circuits for Cloud Servers and Clients Sumio Morioka, Jun Furukawa, Yuichi Nakamura, Kazue Sako (NEC) CAS2011-90 |
Group signature is one of the main theme in recent digital signature studies. The scheme allows users to sign anonymousl... [more] | CAS2011-90 pp.31-36 |
| IT | 2010-09-22 11:20 |
Miyagi | Tohoku Gakuin University | A Sorting-Based Architecture of Finding the First Two Minimum Values Qian Xie, Zhixiang Chen, Satoshi Goto (Waseda Univ.) IT2010-43 |
In this paper we propose a sorting-based architecture of finding the first two minimum values. Given a set of numbers X,... [more] | IT2010-43 pp.57-61 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-26 11:55 |
Tokyo | An FPGA Implementation of Line-Based Architecture 2-Dimensional Discrete Wavelet Transform Using Impulse C Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.) CPSY2009-84 DC2009-81 |
2 Dimensional DiscreteWavelet Transform(2D-DWT) that is used for Image compression on JPEG2000, makes theoretically less... [more] | CPSY2009-84 DC2009-81 pp.147-152 |
|
| VLD | 2010-03-12 15:00 |
Okinawa | An ASIC implementation of a group signature algorithm using two-level behavioral synthesis Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC) VLD2009-128 |
We implemented a group signature algorithm, which enables anonymous digital signature, into an ASIC. To the best of the... [more] | VLD2009-128 pp.175-180 |
|
| SS | 2010-03-08 10:00 |
Kagoshima | Kagoshima Univ. | A framework for the verification of behavior in E-AoSAS++ Han-Myung Chang, Atsushi Sawada, Masami Noro (Nanzan Univ.) SS2009-64 |
One of the most important issues in software design based on aspect oriented software architecture is the verification o... [more] | SS2009-64 pp.97-102 |
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