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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 13:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Test Generation for Alleviating Over-testing of Approximate Multipliers Qilin Wang, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  DC2023-97 |
In this study, we discuss the alleviation of over-testing for approximate circuits. We target a design of approximate mu... [more] | DC2023-97 pp.17-22 |
| SS | 2023-03-14 17:35 |
Okinawa | (Primary: On-site, Secondary: Online) |
SS2022-58 |
(To be available after the conference date) [more] | SS2022-58 pp.67-72 |
| SS | 2023-03-15 14:10 |
Okinawa | (Primary: On-site, Secondary: Online) |
SS2022-68 |
(To be available after the conference date) [more] | SS2022-68 pp.127-132 |
| DC | 2023-02-28 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
A Test Generation Method to Distinguish Multiple Fault Pairs for Improvement of Fault Diagnosis Resolution Yuya Chida, Toshinori Hosokawa (NIhon Univ.), Koji Yamazaki (Meiji Univ.) DC2022-83 |
(To be available after the conference date) [more] | DC2022-83 pp.6-11 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-29 09:40 |
Kumamoto | (Primary: On-site, Secondary: Online) |
A Test Generation Merhod Based on Design for Diagnosability at RTL Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.) VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49 |
(To be available after the conference date) [more] | VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49 pp.43-48 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] | CPSY2022-3 DC2022-3 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:50 |
Online | Online | A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) CPSY2021-57 DC2021-91 |
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] | CPSY2021-57 DC2021-91 pp.73-78 |
| SS, MSS | 2022-01-12 13:40 |
Nagasaki | Nagasakiken-Kensetsu-Sogo-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Akira Fujimoto, Yoshiki Higo, Shinsuke Matsumoto, Shinji Kusumoto (Osaka Univ.), Kazuya Yasuda () MSS2021-53 SS2021-40 |
(To be available after the conference date) [more] | MSS2021-53 SS2021-40 pp.124-129 |
| DC | 2021-12-10 13:00 |
Kagawa | (Primary: On-site, Secondary: Online) |
A Low Power Oriented Multiple Target Test Generation Method Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55 |
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] | DC2021-55 pp.1-6 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| SS, MSS | 2020-01-14 14:15 |
Hiroshima | MSS2019-44 SS2019-28 |
(To be available after the conference date) [more] | MSS2019-44 SS2019-28 pp.19-24 |
|
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| DC | 2018-02-20 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Locating Hot Spots with Justification Techniques in a Layout Design Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80 |
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] | DC2017-80 pp.19-24 |
| DC | 2018-02-20 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test generation method based on k-cycle testing for finite state machines Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81 |
Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] | DC2017-81 pp.25-30 |
| DC | 2017-02-21 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A dynamic test compaction method on low power oriented test generation using capture safe test vectors Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.) DC2016-74 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | DC2016-74 pp.1-6 |
| DC | 2017-02-21 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75 |
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI techn... [more] | DC2016-75 pp.7-10 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Fast Test Pattern Reordering Based on Weighted Fault Coverage Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.) VLD2016-61 DC2016-55 |
Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the ga... [more] | VLD2016-61 DC2016-55 pp.99-104 |
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