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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT)  CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| SDM | 2015-03-02 13:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Invited Talk]
Area dependence of thermal stability factor in perpendicular STT-MRAM analized by bi-directional data flipping model Koji Tsunoda, Masaki Aoki, Hideyuki Noshiro, Yoshihisa Iba, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Akiyoshi Hatada, Masaaki Nakabayashi, Toshihiro Sugii (LEAP) SDM2014-166 |
We report a statistical analysis of the thermal stability factor (delta) for the top-pinned perpendicular magnetic tunne... [more] | SDM2014-166 pp.23-28 |
| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| MRIS, ITE-MMS | 2014-10-03 09:30 |
Niigata | Kashiwazaki energy hall, Niigata | * Daisuke Saida, Naoharu Shimomura, Eiji Kitagawa, Chikayoshi Kamata, Megumi Yakabe, Yuuichi Osawa, Shinobu Fujita, Junichi Ito (Toshiba) MR2014-18 |
(To be available after the conference date) [more] | MR2014-18 pp.27-31 |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| ICD | 2014-04-17 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8 |
We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] | ICD2014-8 pp.39-44 |
| ICD | 2014-04-18 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17 |
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] | ICD2014-17 pp.85-90 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:25 |
Kagoshima | A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93 |
In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel juncti... [more] | CPM2013-116 ICD2013-93 pp.49-53 |
|
| MRIS, ITE-MMS | 2013-07-12 16:35 |
Tokyo | Chuo Univ. | Progress on STT MTJ writing Technology and the Effect on Normally-off Computing Systems Junichi Ito, Hiroaki Yoda, Shinobu Fujita, Naoharu Shimomura, Eiji Kitagawa, Keiko Abe, Kumiko Nomura, Hiroki Noguchi (Toshiba) MR2013-13 |
We propose a new processor using STT-MRAMs as cache memories. It enables “Normally-off computing”, where the processor i... [more] | MR2013-13 pp.37-41 |
| ICD | 2013-04-11 09:50 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions Koji Tsunoda, Hideyuki Noshiro, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Yoshihisa Iba, Akiyoshi Hatada, Masaaki Nakabayashi, Takashi Takenaga, Masaki Aoki, Toshihiro Sugii (LEAP) ICD2013-2 |
A novel magnetic tunnel junction (MTJ) for embedded memory applications such as spin transfer torque magneto-resistive r... [more] | ICD2013-2 pp.5-10 |
| ICD | 2013-04-11 14:20 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique
-- Achieves 1.0ns/200ps Wake-Up/Power-Off Times -- Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno (Tohoku Univ.) ICD2013-6 |
A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque mag... [more] | ICD2013-6 pp.27-32 |
| MRIS, ITE-MMS | 2013-03-08 15:50 |
Aichi | Nagoya Univ. | Thermally assisted switching on magnetic tunnel junctions with perpendicular magnetized TbFe memory layer Yuki Fujisawa, Daiki Yoshikawa, Takeshi Kato, Satoshi Iwata (Nagoya Univ.), Shigeru Tsunashima (NISRI) MR2012-50 |
Perpendicular magnetized [Co/Pd] / MgO / TbFe tunnel junctions whose memory layer, TbFe, exhibits large perpendicular an... [more] | MR2012-50 pp.33-37 |
| ICD | 2012-12-17 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
High-performance STT-MRAM and Its Integration for Embedded Application Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90 |
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] | ICD2012-90 pp.17-20 |
| SDM | 2011-11-11 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of a Fully-Parallel High-Density Nonvolatile TCAM Using MTJ Devices Akira Katsumata, Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.) SDM2011-126 |
(To be available after the conference date) [more] | SDM2011-126 pp.63-68 |
| ICD | 2011-04-18 10:00 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
Trends and Multi-level-cell Technology of Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) ICD2011-1 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magnetic tunnel junctions) was devel... [more] | ICD2011-1 pp.1-5 |
| MRIS, ITE-MMS | 2011-03-11 16:45 |
Aichi | Nagoya Univ. | Thermally Assisted Switching on Magnetic Tunnel Junctions with TbFe Layer Koji Noda, Yuki Fujisawa, Takeshi Kato, Satoshi Iwata (Nagoya Univ.), Shigeru Tsunashima (NISRI) MR2010-63 |
We fabricated perpendicular magnetized magnetic tunnel junctions (MTJs) with a rare earth - transition metal (RE-TM) all... [more] | MR2010-63 pp.47-51 |
| SDM | 2010-11-11 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Trends of Magnetic Memory; Multi-Level-Cell Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) SDM2010-173 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magneto tunnel junctions) was develo... [more] | SDM2010-173 pp.11-15 |
| ED, SDM | 2010-07-02 11:35 |
Tokyo | Tokyo Inst. of Tech. Ookayama Campus | The Impact of Current Controlled-MOS Current Mode Logic /Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation Tetsuo Endoh, Masashi Kamiyanagi, Masakazu Muraguchi, Takuya Imamoto, Takeshi Sasaki (Tohoku Univ.) ED2010-109 SDM2010-110 |
In order to realize Integrated Circuits (IC) with operation over the 10GHz range, conventional CMOS logic face critical ... [more] | ED2010-109 SDM2010-110 pp.257-262 |
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