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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW | 2024-02-29 11:20 |
Okayama | Okayama Prefectural University (Primary: On-site, Secondary: Online) |
Terahertz wave receiving circuit that realizes stable reception by following changes in transmission/reception distance Ryuji Naitou, Yasuaki Monnai (UTokyo)  MW2023-177 |
In a homodyne detection circuit consisting of only one mixer, the detection output depends on the phase of RF and LO, so... [more] | MW2023-177 pp.15-20 |
| MW | 2024-03-01 09:25 |
Okayama | Okayama Prefectural University (Primary: On-site, Secondary: Online) |
A 100GHz-band GaN Transmitter Module with Triple-Multiplier for Beyond 5G Using Terahertz Band Yoshifumi Kawamura, Shimpei Yamashita, Keigo Nakatani, Koji Yamanaka, Yoshitaka Kamo, Kenichi Horiguchi, Tetsuo Kunii, Hirotaka Amasuga (Mitsubishi Electric) MW2023-187 |
The goal of Beyond 5G (B5G) is to achieve ultra-high-speed, large-capacity communications 10 times faster than 5G. In or... [more] | MW2023-187 pp.66-69 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 |
Recently, approximate computing has attracted attention as a method to reduce power and area for error-tolerant applicat... [more] | VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 pp.156-161 |
| SCE | 2023-10-31 09:35 |
Miyagi | RIEC, Tohoku Univ. (Primary: On-site, Secondary: Online) |
Design and demonstration of multipliers using adiabatic quantum-flux-parametron Yu Hoshika, Shohei Takagi, Tomoyuki Tanaka (YNU), Christopher L. Ayala, Nobuyuki Yoshikawa (YNU-IAS) SCE2023-16 |
Adiabatic quantum-flux-parametron (AQFP) logic is an emerging superconducting circuit technology, which is superior in t... [more] | SCE2023-16 pp.21-25 |
| NLP, CAS | 2023-10-07 13:20 |
Gifu | Work plaza Gifu | Proposal and evaluation of a distributed lasso algorithm based on alternating direction multiplier method Naoki Toda, Tsuyoshi Migita, Norikazu Takahashi (Okayama Univ.) CAS2023-55 NLP2023-54 |
Lasso is widely known as a sparse estimation method for regression coefficients in linear regression models, and the Alt... [more] | CAS2023-55 NLP2023-54 pp.111-116 |
| SANE | 2022-12-16 15:05 |
Nagasaki | Nagasaki Public Hall (Primary: On-site, Secondary: Online) |
Application of a Silicon Photomultiplier Detector in Doppler LIDAR Yusuke Aonuma (Tokai Univ.), Takahide Mizuno (JAXA), Makoto Tanaka (Tokai Univ.) SANE2022-85 |
The aim of this study was to increase the receiving sensitivity of Doppler LIDAR (LIght Detection And Ranging) in terms ... [more] | SANE2022-85 pp.110-115 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 15:00 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ) VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have ... [more] | VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 pp.25-30 |
| SCE | 2022-08-09 09:35 |
Online | Online | Design of Energy-Efficient Adiabatic Quantum-Flux-Parametron Multiplier Families Shohei Takagi, Tomoyuki Tanaka (YNU), Christopher Ayala, Nobuyuki Yoshikawa (IAS,YNU) SCE2022-1 |
Adiabatic Quantum Flux Parametron (AQFP) circuits are characterized by a power dissipation of 5 to 6 orders less than CM... [more] | SCE2022-1 pp.1-5 |
| VLD, HWS [detail] | 2022-03-07 10:00 |
Online | Online | A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2021-78 HWS2021-55 |
This paper studies a scheduling algorithm for high-level synthesis that takes into account the difference in delay betwe... [more] | VLD2021-78 HWS2021-55 pp.13-18 |
| VLD, HWS [detail] | 2022-03-07 11:25 |
Online | Online | Design and Measurement of Crypto Processor for Post Quantum Cryptography CRYSTALS-Kyber Taishin Shimada, Makoto Ikeda (Univ. of Tokyo) VLD2021-81 HWS2021-58 |
CRYSTALS-Kyber is one of the public key cryptosystems being considered as a public key cryptosystem after the advent of ... [more] | VLD2021-81 HWS2021-58 pp.31-36 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:45 |
Online | Online | Performance Evaluation of Serial-Parallel Montgomery Multipliers for RNS Hiroyuki Tsubouchi, Mitsunaga Kinjo, Katsuhiko Shimabukuro (Univ. of the Ryukyus) SDM2021-40 ICD2021-11 |
Modulo operations are required in RNS (Residue Number System) which enables to perform highly parallel computation. Also... [more] | SDM2021-40 ICD2021-11 pp.54-57 |
| HWS, VLD [detail] | 2021-03-03 10:25 |
Online | Online | Evaluation on Approximate Multiplier for CNN Calculation Yuechuan Zhang, Masahiro Fujita, Takashi Matsumoto (UTokyo) VLD2020-68 HWS2020-43 |
Improving the accuracy of a convolutional neural network (CNN) typically requires larger hardware with more energy consu... [more] | VLD2020-68 HWS2020-43 pp.7-12 |
| HWS, VLD [detail] | 2021-03-04 09:55 |
Online | Online | High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] | VLD2020-80 HWS2020-55 pp.67-72 |
| SCE | 2020-11-25 14:45 |
Online | Online | Enhanced Operation Frequencies of Bipolar Double-Flux-Quantum Amplifiers Fabricated Using a Nb 10-kA/cm2 Integration Process Yuta Somei, Hiroshi Shimada, Yoshinao Mizugaki (UEC) SCE2020-9 |
A Double-Flux-Quantum Amplifier (DFQA) is a superconducting voltage multiplier that can generate a high-precision voltag... [more] | SCE2020-9 pp.7-11 |
| MW, EST, EMCJ, PEM, IEE-EMC [detail] | 2020-10-23 09:00 |
Online | Online | Electromagnetic and Circuit Combined Simulation for DBM Integrated Orthogonal Dual Modes Resonator Tatsuki Kayashima, Eisuke Nishiyama, Ichihiko Toyoda (Saga Univ.) EMCJ2020-36 MW2020-50 EST2020-38 |
In this study, a simulation approach is applied to a resonator utilizing the nonlinear characteristics of double-balance... [more] | EMCJ2020-36 MW2020-50 EST2020-38 pp.66-71 |
| HWS, VLD [detail] | 2020-03-05 16:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit Jie Li, Yi Guo, Shinji Kimura (Waseda Univ.) VLD2019-120 HWS2019-93 |
Approximate computing (AC) sacrifices accuracy for better hardware performance since it relaxes the requirement of exact... [more] | VLD2019-120 HWS2019-93 pp.151-156 |
| CS, CAS | 2020-02-27 12:10 |
Kumamoto | A Serial Multiplier based on Sequential Subtraction from Maximum Products and Its Negative Number Calculation Method Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Daichi Ikeda (Sanyo Denken), Isao Kayano (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-105 CS2019-105 |
In recent years, digital hearing aids have become widespread, but their battery life is only about several days. To solv... [more] | CAS2019-105 CS2019-105 pp.43-48 |
|
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-24 14:45 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Partial synthesis method based on Column-wise verification for integer multipliers Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2019-89 CPSY2019-87 RECONF2019-79 |
Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be log... [more] | VLD2019-89 CPSY2019-87 RECONF2019-79 pp.211-216 |
| MSS, CAS, SIP, VLD | 2019-07-31 16:45 |
Iwate | Iwate Univ. | Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo, Isao Kayono (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 |
Recently, digital hearing aids with DSP have spread through, but their battery life has remained for only a few days. Fo... [more] | CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 pp.99-104 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-23 14:25 |
Kochi | Kochi University of Technology | Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 |
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] | ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32 pp.151-156 |
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