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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 23  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2011-12-16
Nara NAIST Characterization and Modeling of Drain Overshoot Current in Poly-Si Thin Film Transistors
Toshifumi Ota, Hiroshi Tsuji, Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.) SDM2011-142
Transient characteristics of drain current in poly-Si thin film transistors (TFTs) are investigated experimentally, and ... [more] SDM2011-142
ICD 2011-12-15
Osaka   [Poster Presentation] A Implementation Technique of a Multibit Successive Approximation Register AD Converter
Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2011-107
A multibit SAR(Successive Approximation Register)-ADC is presented.Recent growth of the portable device market requires ... [more] ICD2011-107
ICD 2011-12-15
Osaka   [Poster Presentation] Comparator for A/D converter using time-to-digital converter
Naoki Isobe, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2011-111
 [more] ICD2011-111
VLD 2011-03-04
Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Behavior Verification of a Variable Latency Circuit on FPGA
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2010-142
 [more] VLD2010-142
ICD 2010-12-16
Tokyo RCAST, Univ. of Tokyo [Poster Presentation] Design of Triple-band GPS Receiver
Ikkyun Jo, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.), Takuji Ebinuma (The Univ. of Tokyo) ICD2010-111
This study describes a global positioning system(GPS) adapted fortriple bands(L1,L2,L5). This system uses doubly balance... [more] ICD2010-111
US 2010-10-19
Tokyo Nihon Univ. Directivity Design of Ultrasonic Array Sensor using Reinforcement Learning
Naoki Kotani, Kenji Taniguchi (Osaka Univ.) US2010-75
We propose a method of directivity design based on Reinforcement Learning.
Reinforcement Learning is one of the machine... [more]
VLD 2010-03-12
Okinawa   Performance evaluation of ADDER with Error-Detection-Correction Mechanism
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2009-121
In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum ... [more] VLD2009-121
ICD 2009-12-14
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Process Variation Compensation Technique for 0.5-V Body-Input Comparator
Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-86
This work presents a compensation method for low-voltage body-input comparator to alleviate performance degradation due ... [more] ICD2009-86
ICD 2009-12-14
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] A Design of Parallel Analog-to-Digital Converter Utilizing Process Variations
Hyunju Ham, Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-87
 [more] ICD2009-87
ICD 2009-12-14
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] An evaluation of delay error rate of an adder in terms of clock period
Yuuta Ukon, Atsushi Takahashi, Kenji Taniguchi (Osaka Univ.) ICD2009-91
Currently, digital circuits are mainly realized as synchronous circuits that uses global clocks. In clock-synchronous ci... [more] ICD2009-91
SDM 2009-12-04
Nara NAIST Characteristics of hot hole injection, trapping, and detrapping in gate oxide of poly-Si TFTs
Yoshinari Kamakura (Osaka Univ.), Takashi Himukashi (Osaka Univ./Kansai Univ.), Hiroshi Tsuji, Kenji Taniguchi (Osaka Univ.) SDM2009-157
The hysteresis observed in the transfer characteristics of n-channel poly-Si TFTs are experimentally investigated and po... [more] SDM2009-157
SDM 2009-11-12
Tokyo Kikai-Shinko-Kaikan Bldg. Surface-Potential-Based Drain Current Model for Thin-Film Transistors
Hiroshi Tsuji (Osaka Univ/JST), Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.) SDM2009-138
A new surface-potential-based drain current model for polycrystalline silicon thin-film transistors (poly-Si TFTs) is pr... [more] SDM2009-138
SDM 2009-11-13
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of Self-Heating Effect on the Electrical Characteristics of Nanoscale Transistors
Yoshinari Kamakura, Nobuya Mori (Osaka Univ./JST), Kenji Taniguchi (Osaka Univ.) SDM2009-142
Hot phonon generation and its impact on the current conduction in nanoscale Si-MOSFETs are investigated using numerical ... [more] SDM2009-142
ICD, ITE-IST 2009-10-02
Tokyo CIC Tokyo (Tamachi) A 0.5 V Feedforward Delta-Sigma Modulator with CMOS Inverter-Based Integrator
Jun Wang, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-49
 [more] ICD2009-49
ICD, ITE-IST 2009-10-02
Tokyo CIC Tokyo (Tamachi) Low-Power Zero-IF Full-segment ISDB-T CMOS Tuner with 10th-Order Channel Filters
Takatusugu Kamata (Osaka Univ./RfStream Corp.), Kazunori Okui, Masahiko Fukasawa, Kazuyoshi Tanaka, Go Chyuki (RfStream Corp.), Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2009-57
A zero-IF Tuner IC with wide RF input range (92dB) and low power consumption (528mW in a single 3.3V supply) for full-se... [more] ICD2009-57
ICD 2008-12-12
Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan [Invited Talk] For those who wish to be a integrated circuit designer
Kenji Taniguchi (Osaka Univ.) ICD2008-120
Present-day engineering studies provided at universities and professional continuing education for analog circuit design... [more] ICD2008-120
SDM 2007-12-14
Nara Nara Institute Science and Technology Analysis of Capacitance-Voltage Characteristics of Poly-Si TFTs using Device Simulation
Tsuyoshi Kuzuoka, Hiroshi Tsuji, Masaharu Kirihara, Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.) SDM2007-225
Capacitance-voltage characteristics of short channel Poly-Si TFTs containing only a single grain boundary were investiga... [more] SDM2007-225
SDM, VLD 2007-10-30
Tokyo Kikai-Shinko-Kaikan Bldg. Simulation on the electric conduction of semiconductor with arrayed dopant
Tomohide Terunuma, Takanobu Watanabe (Waseda Univ.), Takahiro Shinada (ASMeW), Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.), Iwao Ohdomari (Waseda Univ.) VLD2007-50 SDM2007-194
 [more] VLD2007-50 SDM2007-194
SDM, VLD 2007-10-30
Tokyo Kikai-Shinko-Kaikan Bldg. Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs
Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.) VLD2007-59 SDM2007-203
We have developed a system consisting of a full-3D process simulator for stress calculation and k·pband calculation... [more] VLD2007-59 SDM2007-203
ICD, ITE-IST 2007-07-27
Hyogo   A Study of Clock and Data Recovery Circuits with Wide Band VCO
Tomoyuki Tanaka (Osaka Univ./Synthesis), Tsukasa Ida, Guechol Kim, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) ICD2007-54
We proposed wide band Clock and Data Recovery circuits (CDR) with VCO-control-voltage recovery block which avoid the loo... [more] ICD2007-54
 Results 1 - 20 of 23  /  [Next]  
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