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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2023-08-01 13:00 |
Hokkaido | Hokkaido Univ. Multimedia Education Bldg. 3F (Primary: On-site, Secondary: Online) |
[Invited Talk]
R and D of Low Power Semiconductor Technology and It's Application Expansions
-- Review R and D of Semiconductor device and LSI for these 43 years -- Koichiro Ishibashi (UEC)  SDM2023-38 ICD2023-17 |
LSI density has been doubling every two years for 64 years, since Moore’s law started in 1959. The presenter began resea... [more] | SDM2023-38 ICD2023-17 pp.14-15 |
| HWS, VLD | 2023-03-01 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Circuit Optimization and Simulation Evaluation for Ultra-Low Voltage of LRPUF Using Manufacturing Variability of Leakage Current Shunkichi Hata, Kimiyoshi Usami (SIT) VLD2022-77 HWS2022-48 |
Low power consumption and low-voltage operation become critical issues to be addressed when PUF (Physically Unclonable F... [more] | VLD2022-77 HWS2022-48 pp.25-30 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 09:45 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Enrei Jo, Rei Miura, Toshinori Hosokawa (Nihon Univ), Masayosi Yoshimura (KSU) CPSY2022-1 DC2022-1 |
In recent years, with the low power design of VLSIs, many low power oriented don't care (X) identification methods and X... [more] | CPSY2022-1 DC2022-1 pp.1-6 |
| ED | 2022-04-21 11:20 |
Online | Online | A High Process Portability All Digital Time domain A/D Converter Takahiro Amada, Cong-Kha Pham (UEC Tokyo) ED2022-6 |
An all digital time domain A/D converter that can be largely synthesized has been proposed. The proposed circuit was des... [more] | ED2022-6 pp.19-22 |
| ASN | 2018-01-31 12:20 |
Oita | Yufugo-kan (Oita) | [Poster Presentation]
Nano wattage ambient temperature sensor circuit for energy harvesting sensor network Shinya Nii, Koichiro Ishibashi (UEC) ASN2017-104 |
In this paper, we propose a nano watt ambient temperature sensor circuit for an energy harvesting sensor network which m... [more] | ASN2017-104 pp.121-126 |
| DC | 2017-02-21 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75 |
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI techn... [more] | DC2016-75 pp.7-10 |
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:00 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A fully on-chip, ultra-low power RC oscillator with current mode architecture for real time clock applications Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 |
A compact and low-power current-mode RC oscillator (RCO) with process, voltage, and temperature (PVT) stability has been... [more] | EMD2016-85 MR2016-57 SCE2016-63 EID2016-64 ED2016-128 CPM2016-129 SDM2016-128 ICD2016-116 OME2016-97 pp.81-86 |
| ICD, CPSY | 2016-12-16 14:20 |
Tokyo | Tokyo Institute of Technology | [Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba) ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] | ICD2016-96 CPSY2016-102 pp.139-144 |
| ICD, CPSY | 2015-12-18 10:00 |
Kyoto | Kyoto Institute of Technology | [Invited Talk]
A Story of a Startup Semiconductor Company, From Creation to Evacuation
-- What to learn in your university life -- Kazuo Taki (Kobe Univ.) ICD2015-85 CPSY2015-98 |
This article shows 10-year experiences on a startup semiconductor design company, originally started from university res... [more] | ICD2015-85 CPSY2015-98 pp.81-82 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| MW (Workshop) |
2013-12-02 - 2013-12-04 |
Overseas | King Mongkut's University of Technology North Bangkok, Thailand | An ultra-low power LNA design using SOTB CMOS devices Hoang Minh Thien, Koichiro Ishibashi (UEC) |
The paper presents a 920MHz Ultra-low power low noise amplifier (LNA) circuit, the first LNA is designed based on the 65... [more] | |
| DC, CPSY (Joint) |
2013-08-02 17:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Design of Variable Stages Pipeline Processor on Superscalar Processor Tomoyuki Nakabayashi, Seiji Miyoshi, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2013-27 |
This paper designs a high performance and low energy superscalar processor using variable stages pipeline (VSP) techniqu... [more] | CPSY2013-27 pp.103-108 |
| SIP, CAS, MSS, VLD | 2013-07-12 10:00 |
Kumamoto | Kumamoto Univ. | Fine Grain Power Gating Based on Controllability Propagation and Power-off Probability Zhe Du, Jin Yu, Shinji Kimura (Waseda Univ.) CAS2013-20 VLD2013-30 SIP2013-50 MSS2013-20 |
Power gating technology has been widely used in VLSI designs for leakage power reduction by cutting off power supply to ... [more] | CAS2013-20 VLD2013-30 SIP2013-50 MSS2013-20 pp.107-112 |
| ICD, ITE-IST | 2013-07-05 13:15 |
Hokkaido | San Refre Hakodate | [Invited Talk]
Design Techniques for High-Performance Continuous-Time Delta-Sigma Modulators Shiro Dosho (Panasonic) ICD2013-37 |
Along with miniaturization of CMOS-LSIs, analog-to-digital converters have been highly developed. Especially, performanc... [more] | ICD2013-37 pp.81-88 |
| VLD, IPSJ-SLDM | 2013-05-16 14:10 |
Fukuoka | Kitakyushu International Conference Center | Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET Shohei Nakamura, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-5 |
Silicon on Thin Buried Oxide (SOTB) technology has an advantage that variation in threshold voltage can be more suppress... [more] | VLD2013-5 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Method to Estimate the Number of Don't-Care Bits with Netlist Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) VLD2012-104 DC2012-70 |
X-filling is often utilized so as to achieve test compression, test power reduction, or test quality improvement etc. i... [more] |
VLD2012-104 DC2012-70 pp.261-266 |
| ICD | 2011-12-16 13:50 |
Osaka | A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers Keisuke Okuno, Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2011-132 |
We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS tr... [more] | ICD2011-132 pp.149-154 |
|
| CPSY | 2011-10-21 09:50 |
Hyogo | Study of Mixed Power Gating on VLIW Processors Yoshifumi Ishii, Weihan Wang, Hideharu Amano (Keio Univ.) CPSY2011-26 |
Power Gating (PG) is an effective way to reduce leakage power that becomes a big issue in LSI designs. There are two way... [more] | CPSY2011-26 pp.7-12 |
|
| VLD | 2011-09-26 14:50 |
Fukushima | University of Aizu | MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) VLD2011-42 |
The optimization techniques for VLSI/PCB placement with larger solution space and more objectives are facing big challen... [more] | VLD2011-42 pp.11-16 |
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