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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICM | 2023-03-17 10:10 |
Okinawa | Okinawa Prefectural Museum and Art Museum (Primary: On-site, Secondary: Online) |
Enhancement of Dialogue in Chatbots to Support Helpdesk Operations Tomoaki Maruyama (Osaka City Univ.), Manato Fujimoto, Shingo Ata (Osaka Metropolitan Univ.)  ICM2022-53 |
Chatbots have been attracting attention in recent years as a means of providing answers to customers' questions in an in... [more] | ICM2022-53 pp.49-54 |
| HWS, VLD [detail] | 2020-03-04 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (UoA) VLD2019-103 HWS2019-76 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2019-103 HWS2019-76 pp.53-58 |
| SDM | 2019-10-24 10:50 |
Miyagi | Niche, Tohoku Univ. | Low temperature formation of PdErSi/Si(100) for Schottky barrier source and drain MOSFET applications Rengie Mark D. Mailig, Yuichiro Aruga, Min Gee Kim, Shun-ichiro Ohmi (Tokyo Tech) SDM2019-61 |
In this report, the effects of the TiN encapsulating layer on the low temperature formation of the PdErSi/Si(100) with d... [more] | SDM2019-61 pp.39-43 |
| VLD, HWS (Joint) |
2018-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2017-107 pp.109-114 |
| VLD | 2017-03-01 14:50 |
Okinawa | Okinawa Seinen Kaikan | Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104 |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] | VLD2016-104 pp.13-18 |
| CAS | 2014-02-07 13:30 |
Kanagawa | Nippon Maru Training center | A probe epidemic transmission considering mobility characteristics of nodes in DTNs Shigeto Sawabe, Arata Kato, Naoyuki Karasawa, Keisuke Nakano (Niigata Univ.) CAS2013-87 |
In this report, we consider communication characteristics of the probe epidemic transmission in Delay Tolerant Network w... [more] | CAS2013-87 pp.71-74 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 11:25 |
Aomori | A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) VLD2013-59 ICD2013-83 IE2013-59 |
Variable delay elements are often used in various types of high-speed integrated circuits, mainly intended for delay c... [more] |
VLD2013-59 ICD2013-83 IE2013-59 pp.71-76 |
|
| NS, IN (Joint) |
2013-03-08 15:10 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | A Study on DTN Routing for Underwater Acoustic Sensor Networks Tadashi Yamazaki, Atsuhiro Takano, Jiro Katto (Waseda Univ.), Hayato Kondo (Tokyo Univ. of Marine Science & Tech.) NS2012-255 |
Underwater Sensor Networks have received growing interests recently, which can monitor and collect underwater environmen... [more] | NS2012-255 pp.523-528 |
| VLD | 2012-03-06 14:25 |
Oita | B-con Plaza | Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability Yosuke Haruta, Mineo Kaneko (JAIST) VLD2011-127 |
With the progress of fabrication-process technology, the variation of signal transmission delay due to variations in pro... [more] | VLD2011-127 pp.43-48 |
| AI, IPSJ-ICS, JSAI-KBS | 2009-03-03 14:00 |
Miyagi | Laforet Zao Resort & Spa | Study on Emergent Behaviors of Crowded People in a Station through an Agent-based simulation Model Kazuki Satoh, Toru Takahashi, Takashi Yamada, Takao Terano (Tokyo Inst. of Tech.) |
This study examines a state of the refuge of the walker of the station yard in the emergency by agent-based simulation. ... [more] | AI2008-78 pp.81-86 |
| CAS | 2008-02-01 09:25 |
Okinawa | A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-95 |
In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. Des... [more] | CAS2007-95 pp.7-12 |
|
| VLD, IPSJ-SLDM | 2007-05-11 10:20 |
Kyoto | Kyodai Kaikan | A Clock Deskew Method using PDE with Discrete Delay Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9 |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2007-9 pp.13-18 |
| ICD, VLD | 2007-03-08 11:10 |
Okinawa | Mielparque Okinawa | A Clock Deskew Method Using Statisical Presumption Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC) |
In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] | VLD2006-126 ICD2006-217 pp.43-48 |
| CQ, MVE (Joint) |
2007-01-26 10:30 |
Fukuoka | Asia-pacific Import Mart | [Fellow Memorial Lecture]
Approachs on CPD：Continuing Professional Development
-- Trial of CPD member system -- Hisao Yamamoto (Musashi Tech) CQ2006-89 MVE2006-77 |
The social necessity of Continuing Professional Development (CPD) for engineers has arisen and it’s supporting environme... [more] | CQ2006-89 MVE2006-77 pp.59-60(CQ), pp.37-38(MVE) |
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