Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2013-134
Characterization of Random Telegraph Noise using Inhomogeneous Ring Oscillator
Shohei Nishimura, Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 1 - 6
VLD2013-135
Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay
Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 7 - 12
VLD2013-136
Fast Simulation of Multilayered Power Distribution Networks by Using Conformal Mesh Model and Block-Type Leapfrog Scheme
Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
pp. 13 - 18
VLD2013-137
nMOS Dynamic Shift Registers for Driver Circuit of Small LCD and Their Evaluations
Shinji Higa, Tomohiro Kurita, Shuji Tsukiyama (Chuo Univ.)
pp. 19 - 24
VLD2013-138
On a Statistical Method for Analyzing Lifetime of Series-Connected Batteries
Daisuke Sasaki, Shuji Tsukiyama, Mariko Matsunaga (Chuo Univ.), Shingo Takahashi (NEC)
pp. 25 - 30
VLD2013-139
Improved scan-based side-channel attack on the LED block cipher independent of scan structure
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 31 - 36
VLD2013-140
Latch-based AES Encryption Circuit Against Fault Analysis
Youhua Shi, Hiroaki Taniguchi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)
pp. 37 - 42
VLD2013-141
Secure scan design using improved random order scans and its evaluations
Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 43 - 48
VLD2013-142
An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing
Yusaku Yamamoto, Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 49 - 54
VLD2013-143
An Effective Solution Space for Simulated Annealing
Hiroshi Tezuka, Kunihiro Fujiyoshi (TUAT)
pp. 55 - 60
VLD2013-144
Parallel Tabu Search for the Motif Extraction Problem in Molecular Biology and its GPGPU Implementation
Yuki Tanihara, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 61 - 66
VLD2013-145
An Approach of Rate-Distortion Optimized Quantization and its Evaluation
Genki Moriguchi, Hajime Sawano, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.)
pp. 67 - 72
VLD2013-146
An Hardware Implementation of Motion Estimation Technology Using High Level Synthesis
Shota Nagai, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.)
pp. 73 - 77
VLD2013-147
Effect of Correlated Stochastic Numbers on Calculation Accuracy
Shota Ishii, Daiki Sunamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 79 - 84
VLD2013-148
[Invited Talk]
Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm
Shuhei Sota (Toshiba Microelectronics), Taiga Uno, Masanari Kajiwara, Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Ryota Aburada, Toshiya Kotani (Toshiba), Kei Nakagawa, Tamaki Saito (Toshiba Microelectronics)
p. 85
VLD2013-149
Local Pattern Modification Method for Lithographical ECO in Double Patterning
Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba)
pp. 87 - 92
VLD2013-150
Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing
Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech.), Chikaaki Kodama (TOSHIBA)
pp. 93 - 98
VLD2013-151
Self-Aligned Double and Quadruple Patterning-Aware Grid Routing
Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba)
pp. 99 - 104
VLD2013-152
Exposure source optimization by clustering for lithography
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba)
pp. 105 - 110
VLD2013-153
[Memorial Lecture]
A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips
Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ.), Tsung-Yi Ho (National Cheng-Kung Univ.)
pp. 111 - 112
VLD2013-154
[Memorial Lecture]
Co-simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki (Mie Univ.), Eric Rotenberg (NCSU), Toshio Kondo (Mie Univ.)
p. 113
VLD2013-155
[Memorial Lecture]
HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines
Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
pp. 115 - 118
VLD2013-156
Area-Efficient Soft-Error Tolerant Datapath Design Based on Aggressive Resource Sharing
Junghoon Oh, Mineo Kaneko (JAIST)
pp. 119 - 124
VLD2013-157
Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects
Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 125 - 130
VLD2013-158
Analysis of Radiation-Induced Errors in PLL based on Behavioral Modeling
SinNyoung Kim (Kyoto Univ.), Tomohiro Fujita (Ritsumeikan Univ.), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.)
pp. 131 - 136
VLD2013-159
Inductive-Coupling Interface for Multiple-Memory Chip Stacking
Mitsuko Saito, Tadahiro Kuroda (Keio Univ.)
pp. 137 - 140
VLD2013-160
Investigation of thermal monitor for applying to Dynamic Voltage Scaling in SOTB
Tatsuya Wada, Kimiyoshi Usami (Shibaura Inst. of Tech)
pp. 141 - 146
VLD2013-161
Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits
Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.)
pp. 147 - 151
VLD2013-162
Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB)
Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech)
pp. 153 - 158
VLD2013-163
Post –Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI
Tatsunori Kubo, Mineo Kaneko (JASIT)
pp. 159 - 163
VLD2013-164
A Design Method of Mixed Synchronous-Asynchronous Circuit
Kotaro Kato, Mineo Kaneko (JAIST)
pp. 165 - 170
VLD2013-165
Function Code Extraction from RTL Property for Reuse
Msaato Tatsuoka, Toshiaki Aoki, Mineo Kaneko (JAIST)
pp. 171 - 176
VLD2013-166
A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design
Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.)
pp. 177 - 182
VLD2013-167
Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling
Tatsuya Masui, Yukihide Kohira (Univ. of Aizu)
pp. 183 - 188
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.