Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2015-1
[Special Talk]
Semiconductor Innovation seen from Makimoto's Wave and its Impact
Tsugio Makimoto (SSIS)
pp. 1 - 6
RECONF2015-2
Power optimization of low-power reconfigurable accelerator CMA-SOTB
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano (Keio Univ.)
pp. 7 - 12
RECONF2015-3
Evaluation of the third Flex Power FPGA chip in SOTB technology
Masakazu Hioki, Yasuhiro Ogasahara, Hanpei Koike (AIST)
pp. 13 - 16
RECONF2015-4
An Area Optimization of 3D FPGA with high speed inter-layer communication link
Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
pp. 17 - 22
RECONF2015-5
A Classification Hardware with Hierarchical Multiple Scan Window Sizes for Colorectal Endoscopic Diagnosis
Takumi Okamoto, Tetsushi Koide, Tatsuya Shimizu, Koki Sugi, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.)
pp. 23 - 28
RECONF2015-6
Consideration for Visual Word Feature Transformation Hardware based on Bag-of-Features
Koki Sugi, Tetsushi Koide, Tatsuya Shimizu, Takumi Okamoto, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.)
pp. 29 - 34
RECONF2015-7
High Speed Calculation of Convex Hull in 2D Images using FPGA
Kahori Kemmotsu, Kenji Kanazawa, Yamato Mori (Univ. of Tsukuba), Noriyuki Aibe (SUSUBOX), Moritoshi Yasunaga (Univ. of Tsukuba)
pp. 35 - 40
RECONF2015-8
ROS compliant componentizing of image processing hardware on a Programmable SoC
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 41 - 46
RECONF2015-9
Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA
Keisuke Hirofuji, Ryo Okuda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
pp. 47 - 52
RECONF2015-10
Realization of FPGA Control Processing with Functional Safety
Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Yudai Shirakura, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
pp. 53 - 57
RECONF2015-11
An arithmetic design approach with diversity and redundancy for FPGAs
Yudai Shirakura, Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
pp. 59 - 63
RECONF2015-12
Towards the Fastest FPGA-based Sorting Hardware in the World
Ryohei Kobayashi, Kenji Kise (Tokyo Tech)
pp. 65 - 70
RECONF2015-13
[Invited Talk]
Reliability on Integrated Circuits
Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
p. 71
RECONF2015-14
A SW/HW Interface Implementation Method in the System Design Environment for Programmable SoCs
Yusuke Tani, Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
pp. 73 - 78
RECONF2015-15
A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications
Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST)
pp. 79 - 84
RECONF2015-16
Implementation and Applications of An Efficient Parallel Architecture for Matrix Calculations
Yuki Murakami, Naohito Nakasato, S. Sedukhin (Univ. of Aizu)
pp. 85 - 90
RECONF2015-17
A Deep Convolutional Neural Network Based on Nested Residue Number System
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.)
pp. 91 - 96
RECONF2015-18
A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST)
pp. 97 - 102
RECONF2015-19
FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3
Yohei Hori, Toshihiro Katashita (AIST)
pp. 103 - 108
RECONF2015-20
Introduction to 2015 FPGA Trax contest
Yasunori Osana (Univ. of the Ryukyus), Tomonori Izumi (Ritsmeikan Univ.), Takefumi Miyoshi (e-trees), Hiroki Nakahara (Ehime Univ.)
pp. 109 - 112
RECONF2015-21
Real Chip evaluation of a dynamically reconfigurable processor MuCCRA-4 with ST micro 28nm Process
Hideharu Amano, Toru Katagiri (Keio Univ.)
pp. 113 - 118
RECONF2015-22
On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors
Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST)
pp. 119 - 124
RECONF2015-23
Tile-base PLA Cell with Uni-Switch Structure
Atsushi Nanri, Kosuke Murakami, Daijiro Murooka, Takuya Hirata, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 125 - 130
RECONF2015-24
High-speed scrubbing on optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
pp. 131 - 134
RECONF2015-25
Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch
Naoya Tokusada, Tetsuo Hironaka, Kazuya Tanigawa (HCU), Takashi Ishiguro (Taiyo Yuden)
pp. 135 - 140
RECONF2015-26
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device
Tieyuan Pan, Zhu Li, Lian Zeng, Takahiro Watanabe (Waseda Univ.), Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 141 - 146
RECONF2015-27
A Technology Mapping Method for Scalable Logic Module
Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)
pp. 147 - 152
RECONF2015-28
Data-Triggered Breakpoint for In-Circuit Debug without Re-implementation
Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura (Fujitsu Labs.)
pp. 153 - 158
RECONF2015-29
High-Level Synthesis Compiler for Hierarchical and Modular Design of Stream Computing Cores
Kentaro Sano, Ryo Ito, Keisuke Sugawara, Satoru Yamamoto (Tohoku Univ.)
pp. 159 - 164
RECONF2015-30
An Implementation and Evaluation of A Generic Interface between PC and FPGA with AHCI
Takefumi Miyoshi, Satoshi Funada (e-trees)
pp. 165 - 170
RECONF2015-31
FPGA design using high-level description
-- sound synthesizer implementation and its evaluation --
Fang-Xiang Gao, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. Tsukuba)
pp. 171 - 176
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.