Tue, Dec 1 PM
12:45 - 13:35 |
(1)
DC |
12:45-13:10 |
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan  VLD2015-38 DC2015-34 |
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST) |
(2)
VLD |
13:10-13:35 |
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit VLD2015-39 DC2015-35 |
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) |
Tue, Dec 1 PM
12:45 - 13:35 |
(3)
RECONF |
12:45-13:10 |
Triple modular redundancy on a parallel-operation-oriented optically reconfigurable gate array RECONF2015-47 |
Yoshizumi Ito, Minoru Watanabe (Shizuoka Univ.) |
(4)
RECONF |
13:10-13:35 |
Fault tolerance of an inversion configuration method on an optically configurable gate array RECONF2015-48 |
Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.) |
Tue, Dec 1 PM
12:45 - 13:35 |
(5)
CPSY |
12:45-13:10 |
Performance Evaluations of Document-Oriented Databases using Remote GPU Cluster CPSY2015-61 |
Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(6)
CPSY |
13:10-13:35 |
A study of GPU acceleration of "source" part in Hall-thruster simulation CPSY2015-62 |
Takaaki Miyajima, Shinatora Cho, Naoyuki Fujita (JAXA) |
| |
13:35-13:50 |
Break ( 15 min. ) |
Tue, Dec 1 PM
13:50 - 15:30 |
(7)
ICD |
13:50-14:40 |
[Invited Talk]
IC Chip Authentication and Guarantee
-- As Root Problems of Hardware Security -- CPM2015-126 ICD2015-51 |
Makoto Nagata (Kobe Univ.) |
(8)
ICD |
14:40-15:30 |
[Invited Talk]
Video Coding Hardware Technologies for Distributing 4K/8K Ultra High Definition Images CPM2015-127 ICD2015-52 |
Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu (NTT) |
Tue, Dec 1 PM
13:50 - 15:30 |
(9)
RECONF |
13:50-14:15 |
Partial Recofniguration for Accelerator-in-switch RECONF2015-49 |
Hideharu Amano, Yuichi Sakurai, Chiharu Tsuruta (Keio Univ.) |
(10)
RECONF |
14:15-14:40 |
Dynamic Reconfigurable PLA on FPGA and DSL-based Design Methodology RECONF2015-50 |
Takefumi Miyoshi (wasalabo/e-trees), Hiroki Nakahara (ehime university), Satoshi Funada (e-trees) |
| (11) |
14:40-15:05 |
|
(12)
CPSY |
15:05-15:30 |
Development and Evaluation of Simulator for Cellular Neural Network CPSY2015-63 |
Tomoya Kameda (NAIST), Mutsumi Kimura (Ryukoku Univ.), Yasuhiko Nakashima (NAIST) |
Tue, Dec 1 PM
13:50 - 15:30 |
(13)
DC |
13:50-14:15 |
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories VLD2015-40 DC2015-36 |
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) |
(14)
DC |
14:15-14:40 |
A study on multiple path selection conditions in delay testing using design-for-testability circuit VLD2015-41 DC2015-37 |
Mori Ryosuke, Yotsuyanagi Hiroyuki, Hashizume Masaki (Tokushima Univ.) |
(15)
DC |
14:40-15:05 |
On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines VLD2015-42 DC2015-38 |
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
(16)
VLD |
15:05-15:30 |
Fast Monte Carlo based timing yield calculation VLD2015-43 DC2015-39 |
Hiromitsu Awano, Takashi Sato (Kyoto Univ.) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Tue, Dec 1 PM
15:45 - 16:45 |
| (17) |
15:45-16:45 |
[Fellow Memorial Lecture]
Improving System Dependability by VLSI Test Technology VLD2015-44 CPM2015-128 ICD2015-53 CPSY2015-64 DC2015-40 RECONF2015-51 |
Seiji Kajihara (KIT) |
| |
16:45-17:00 |
Break ( 15 min. ) |
Tue, Dec 1 PM
17:00 - 18:00 |
| (18) |
17:00-18:00 |
[Fellow Memorial Lecture]
Reconfigurable Chips, High-Level Synthesis, and EDA Business |
Kazutoshi Wakabayashi (NEC) |
Wed, Dec 2 AM
09:30 - 11:00 |
| |
- |
|
| |
11:00-11:15 |
Break ( 15 min. ) |
Wed, Dec 2 AM
11:15 - 12:30 |
(19)
VLD |
11:15-11:40 |
Improved Method of Simulated Annealing for Unreachable Solution Space VLD2015-45 DC2015-41 |
Hiroyuki Nakano, Kunihiro Fujiyoshi (TUAT) |
(20)
VLD |
11:40-12:05 |
On applications of Monte-Carlo tree search algorithm for CAD problems VLD2015-46 DC2015-42 |
Yusuke Matsunaga (Kyushu Univ.) |
| (21) |
12:05-12:30 |
|
Wed, Dec 2 AM
11:15 - 12:30 |
(22)
RECONF |
11:15-11:40 |
A Study of HW/SW Co-design Framework based on the Virtualization Technology RECONF2015-52 |
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(23)
RECONF |
11:40-12:05 |
A Software-Oriented Design and Synthesis Platform for a Construction of Real-Time Systems on Programmable SoCs RECONF2015-53 |
Takuya Hatayama, Yusuke Tani, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) |
(24)
VLD |
12:05-12:30 |
A Study on DVFS for Heterogeneous Task Set VLD2015-47 DC2015-43 |
Mineo Kaneko (JAIST) |
Wed, Dec 2 AM
11:15 - 12:30 |
(25)
CPSY |
11:15-11:40 |
A C Framework for Integrating Algorithm Description and CGRA Implementation CPSY2015-65 |
Yasuhiko Nakashima (NAIST) |
(26)
CPSY |
11:40-12:05 |
Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM CPSY2015-66 |
Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) |
(27)
CPSY |
12:05-12:30 |
A proposal of the light field image compression and decompression using HEVC CPSY2015-67 |
Takamasa Mitani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) |
| |
12:30-13:45 |
Break ( 75 min. ) |
Wed, Dec 2 PM
13:45 - 15:25 |
(28)
VLD |
13:45-14:25 |
[Invited Talk]
Towards Getting Your Paper Accepted at International Conferences
-- Based on Experiences of Studying Abroad and Serving as a Program Committee Member -- VLD2015-48 DC2015-44 |
Yuko Hara-Azumi (Tokyo Tech) |
(29)
VLD |
14:25-14:55 |
[Invited Talk]
Taipei Report VLD2015-49 DC2015-45 |
Yasuhiro Takashima (Univ. of Kitakyushu) |
(30)
VLD |
14:55-15:25 |
[Invited Talk]
EDA Research Activities in The University of Texas at Austin VLD2015-50 DC2015-46 |
Tetsuaki Matsunawa (Toshiba) |
Wed, Dec 2 PM
13:45 - 15:25 |
(31)
CPSY |
13:45-14:10 |
A Preliminary Evaluation of Linear Network Using ThruChip Interface CPSY2015-68 |
Akio Nomura, Hiroki Matsutani, Yasuhiro Take (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Technology), Tadahiro Kuroda, Hideharu Amano (Keio Univ.) |
(32)
CPSY |
14:10-14:35 |
CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture CPSY2015-69 |
Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
(33)
CPSY |
14:35-15:00 |
Performance Evaluation of K-best Viterbi Decoder for IoT Applications CPSY2015-70 |
Thi Hong Tran (NAIST), Dwi Rahma Ariyani, Lina Alfaridah ZH (Andalas Univ.), Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima (NAIST) |
(34)
RECONF |
15:00-15:25 |
Problems that occur in FPGAs communication
-- Cautionary point of PCIe Gen3 -- RECONF2015-54 |
Hirotaka Takayama, Yoshiki Yamaguchi (Tsukuba Univ.) |
Wed, Dec 2 PM
13:45 - 15:25 |
(35)
ICD |
13:45-14:10 |
Design of low power AFE circuit supporting IR array sensor for human detection CPM2015-129 ICD2015-54 |
Shota Ueguchi (Ritsumeikan Univ.), Toshio Kumamoto (Osaka Sangyo Univ.), Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.) |
(36)
ICD |
14:10-14:35 |
A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique CPM2015-130 ICD2015-55 |
Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) |
(37)
ICD |
14:35-15:00 |
Study on a tolerance for process variability in Single Slope ADC using interpolative TDC CPM2015-131 ICD2015-56 |
Kaihei Hotta, Kenichi Ohhata (Kagishima Univ.) |
(38)
ICD |
15:00-15:25 |
EMS Evaluation of Adaptively-Tuned Supply-Resonnace Suppression Filter CPM2015-132 ICD2015-57 |
Kohki Taniguchi, Noriyuki Miura, Makoto Nagata (Kobe Univ.) |
Wed, Dec 2 PM
15:25 - 15:55 |
| |
- |
|
Wed, Dec 2 PM
15:55 - 18:00 |
| (39) |
15:55-16:20 |
|
(40)
VLD |
16:20-16:45 |
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits VLD2015-51 DC2015-47 |
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
(41)
VLD |
16:45-17:10 |
Layout Decomposition into L-Shaped Parts for Variable Shaped-Beam Mask Writer VLD2015-52 DC2015-48 |
Katsuya Hoshi, Kunihiro Fujiyoshi (TUAT) |
(42)
VLD |
17:10-17:35 |
Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning VLD2015-53 DC2015-49 |
Takeshi Ihara, Atsushi Takahashi (Tokyo Tech) |
(43)
VLD |
17:35-18:00 |
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs VLD2015-54 DC2015-50 |
Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Wed, Dec 2 PM
15:55 - 18:00 |
(44)
ICD |
15:55-16:20 |
Dynamic Frame-rate Optimization for Low Energy Object Tracking CPM2015-133 ICD2015-58 |
Yusuke Inoue, Takatsugu Ono, Koji Inoue (Kyushu Univ.) |
| (45) |
16:20-16:45 |
|
| (46) |
16:45-17:10 |
|
(47)
VLD |
17:10-17:35 |
An FPGA implementation of real-time position and pose measurement for robotic head VLD2015-55 DC2015-51 |
Masahiro Matsumoto, Kazuhiro Shimonomura (Ritsumeikan) |
(48)
RECONF |
17:35-18:00 |
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope RECONF2015-55 |
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.), Hiroyuki Nakanishi (Kagoshima Univ.), Kazumasa Iwai (NICT), Tohru Nagao (Ehime Univ) |
Wed, Dec 2 PM
15:55 - 18:00 |
(49)
VLD |
15:55-16:20 |
A low-power soft error tolerant latch scheme on 15nm process VLD2015-56 DC2015-52 |
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) |
(50)
VLD |
16:20-16:45 |
Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating VLD2015-57 DC2015-53 |
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
(51)
CPSY |
16:45-17:10 |
An implementation and preliminary evaluation of a dynamic body bias control scheme for a low power micro controller using SOTB MOSFET CPSY2015-71 |
Hayate Okuhara (Keio Univ.), Tomoaki Koide (UEC), Johannes maximilian kuehn, Akram Ben Ahmed (Keio Univ.), Koichiro Ishibashi (UEC), Hideharu Amano (Keio Univ.) |
(52)
ICD |
17:10-17:35 |
The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit CPM2015-134 ICD2015-59 |
Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP) |
(53)
ICD |
17:35-18:00 |
An Energy-Autonomous, Disposable Supply-Sensing Biosensor Platform Using Bio Fuel Cell and 0.25μm CMOS 0.23V Ring Oscillator and Proximity Transmitter for Big-Data-Based Healthcare CPM2015-135 ICD2015-60 |
Kiichi Niitsu (Nagoya Univ./JST), Atsuki Kobayashi, Takashi Ando (Nagoya Univ.), Yudai Ogawa, Matsuhiko Nishizawa (Tohoku Univ.), Kazuo Nakazato (Nagoya Univ.) |
Thu, Dec 3 AM
09:45 - 10:35 |
(54)
VLD |
09:45-10:10 |
Hardware Trojan Identification based on Netlist Features using SVM VLD2015-58 DC2015-54 |
Kento Hasegawa, Oya Masaru, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(55)
VLD |
10:10-10:35 |
A Quantitative Criterion of Gate-Level Netlist Vulnerability VLD2015-59 DC2015-55 |
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Thu, Dec 3 AM
09:20 - 10:35 |
(56)
RECONF |
09:20-09:45 |
Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System RECONF2015-56 |
Koki Sugi, Tetsushi Koide, Tatsuya Shimizu, Takumi Okamoto, Anh-Tuan Hoang, Hikaru Sato, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Toshida, Hiroshi Mieno (Hiroshima General Hospital), Shinji Tanaka (Hiroshima Univ.) |
(57)
RECONF |
09:45-10:10 |
Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract RECONF2015-57 |
Tatsuya Shimizu, Tetsushi Koide, Anh-Tuan Hoang, Koki Sugi, Takumi Okamoto, Hikaru Sato, Toru Tamaki, Bisser Raytchev, Kazuhumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital), Shinji Tanaka (Hiroshima Univ.) |
(58)
RECONF |
10:10-10:35 |
High-level synthesis of an image-based human detection FPGA system with a machine learning technique RECONF2015-58 |
Ryo Fujita, Masahito Oishi, Yoshiki Hayashida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
Thu, Dec 3 AM
09:20 - 10:35 |
(59)
DC |
09:20-09:45 |
A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems VLD2015-60 DC2015-56 |
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(60)
VLD |
09:45-10:10 |
Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs VLD2015-61 DC2015-57 |
Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(61)
VLD |
10:10-10:35 |
An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components VLD2015-62 DC2015-58 |
Junghoon Oh, Mineo Kaneko (JAIST) |
| |
10:35-10:50 |
Break ( 15 min. ) |
Thu, Dec 3 AM
10:50 - 12:30 |
(62)
CPM |
10:50-11:40 |
[Invited Talk]
Development of Via Structures in IC Package Substrates for Impedance Reduction CPM2015-136 ICD2015-61 |
Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani (Fujitsu Lab.) |
(63)
CPM |
11:40-12:30 |
[Invited Talk]
A New Concept of Memory-Logic Conjugated System and It's Spreading
-- Dynamic Reconfiguration System Composed with Memory -- CPM2015-137 ICD2015-62 |
Kanji Otsuka, Youichi Sato (Meisei Univ.), Jun-ichi Kasai (MIRAI) |
Thu, Dec 3 AM
10:50 - 12:30 |
(64)
DC |
10:50-11:15 |
On Correction of Temperature Influence to Delay Measurement in FPGAs VLD2015-63 DC2015-59 |
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) |
(65)
DC |
11:15-11:40 |
Construction and Evaluation of Three-Dimensional Heat Transfer Simulator for LSI Packages VLD2015-64 DC2015-60 |
Shougo Watanabe, Takashi Omura, Yuki Kitagawa, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.) |
(66)
VLD |
11:40-12:05 |
Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan VLD2015-65 DC2015-61 |
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
(67)
VLD |
12:05-12:30 |
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA VLD2015-66 DC2015-62 |
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Thu, Dec 3 AM
10:50 - 12:30 |
(68)
CPSY |
10:50-11:15 |
Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment CPSY2015-72 |
Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) |
(69)
CPSY |
11:15-11:40 |
Logic Design of A Single-Flux-Quantum Microprocessor CPSY2015-73 |
Koki Ishida, Tomonori Tsuhata (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono, Koji Inoue (Kyushu Univ.) |
(70)
CPSY |
11:40-12:05 |
Accuracy Analysis of Machine Learning based Performance Modeling for Microprocessors CPSY2015-74 |
Yoshihiro Tanaka, Takatsugu Ono, Koji Inoue (Kyushu Univ.) |
(71)
CPSY |
12:05-12:30 |
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II CPSY2015-75 |
Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) |
| |
12:30-13:45 |
Break ( 75 min. ) |
Thu, Dec 3 PM
13:45 - 15:00 |
(72)
VLD |
13:45-14:10 |
Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI VLD2015-67 DC2015-63 |
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) |
(73)
VLD |
14:10-14:35 |
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits VLD2015-68 DC2015-64 |
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) |
| (74) |
14:35-15:00 |
|
Thu, Dec 3 PM
13:45 - 15:25 |
(75)
DC |
13:45-14:10 |
An M by N Algorithm Using Multiple Target Test Generation for Static Test Compaction VLD2015-69 DC2015-65 |
Yuya Hara, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon University), Masayoshi Yoshimura (Kyoto Sangyo university) |
(76)
DC |
14:10-14:35 |
An approach to LFSR/MISR seed generation for delay fault BIST VLD2015-70 DC2015-66 |
Daichi Shimazu, Satishi Ohtake (Oita Univ.) |
(77)
DC |
14:35-15:00 |
Design of BIST with soft error resilience for testing FPGAs VLD2015-71 DC2015-67 |
Hiroki Ueda, Daichi Shimadu, Satoshi Ohtake (Oita univ.) |
(78)
DC |
15:00-15:25 |
Easily-testable Carry Select Adder with Online Error Detection Capability VLD2015-72 DC2015-68 |
Nobutaka Kito (Chukyo Univ.) |
Thu, Dec 3 PM
13:45 - 15:25 |
(79)
VLD |
13:45-14:10 |
Fast and Accurate Estimation of Execution Cycles for ARM Architecture VLD2015-73 DC2015-69 |
Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ) |
(80)
VLD |
14:10-14:35 |
Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement VLD2015-74 DC2015-70 |
Junya Goto, Nagisa Ishiura (K.G.) |
(81)
VLD |
14:35-15:00 |
Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses VLD2015-75 DC2015-71 |
Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.) |
(82)
VLD |
15:00-15:25 |
A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories VLD2015-76 DC2015-72 |
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
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