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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2021-01-28 14:05 |
Online | Online | [Invited Talk]
Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance Kazuki Monta (Kobe Univ.)  SDM2020-51 |
In semiconductor integrated circuits, power signal integrity(PSI) and electromagnetic compatibility caused by power supp... [more] | SDM2020-51 pp.8-12 |
| EMCJ, MW, EST, IEE-EMC [detail] | 2019-10-25 16:55 |
Miyagi | Tohoku Gakuin University(Conf. Room 2, Eng. Bldg. 1) | A Study of Decoupling Capacitor Implementation by PSD Method Using RBF Interpolation for Meta-modeling Masashi Kawakami (Akita Prefectural Univ.), Yoshiki Kayano, Fengchao Xiao (UEC), Teruo Tobana (Akita Prefectural Univ.), Yoshio Kami (UEC), Kohei Akimoto, Yoji Isota (Akita Prefectural Univ.) EMCJ2019-70 MW2019-99 EST2019-78 |
This report newly attempt to propose a multi-objective satisfactory design method, Preference Set-based Design (PSD) to... [more] | EMCJ2019-70 MW2019-99 EST2019-78 pp.187-191 |
| EMCJ, IEE-EMC, IEE-MAG | 2018-11-22 16:20 |
Overseas | KAIST | [Invited Talk]
Statistical Eye-diagram Estimation Method Considering Power/Ground Noise Generated by Simultaneous Switching Output Buffers Youngwoo Kim, Junyong Park, Kyungjun Cho, Joungho Kim (KAIST) EMCJ2018-84 |
In the high-speed channel, non-linear power/ground noise generated by simultaneous switching buffer outputs (SSOs) noise... [more] | EMCJ2018-84 pp.79-80 |
| EMCJ | 2018-07-27 13:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Analysis of Suppression Mechanism of Power-bus Resonance Using Lossy Resonator Filter with Pi Equivalent Circuits Sho Kanao, Iokibe Kengo, Yoshitaka Toyota (Okayama Univ.) EMCJ2018-27 |
Power-bus resonance of printed circuit board causes propagation of electromagnetic noise and detraction of power integri... [more] | EMCJ2018-27 pp.31-36 |
| EMCJ, IEE-EMC, IEE-MAG | 2017-05-19 11:15 |
Overseas | Nanyang Technological University | Power Distribution Network Virtual Prototyping
-- A Demonstration of Pre-layout Design, Simulation & Measurement -- Jun Wu Zhang, Eng Kee Chua, Kye Yak See (NTU) EMCJ2017-18 |
This work presents a demonstration and validation on Power Distribution Network (PDN) ＾virtual prototyping￣ design proce... [more] | EMCJ2017-18 pp.63-66 |
| EMCJ, IEE-EMC, IEE-MAG | 2017-05-19 13:20 |
Overseas | Nanyang Technological University | [Invited Talk]
2.5D Method of Modeling and Simulation for Signal/Power Integrity of High Speed Electronics En-Xiao Liu, Siping Gao, Hui Min Lee (A*STAR IHPC) EMCJ2017-19 |
Electromagnetic characteristics related to signal integrity (SI), power integrity (PI) and EMC has become an essential d... [more] | EMCJ2017-19 p.67 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Invited Talk]
Development of Via Structures in IC Package Substrates for Impedance Reduction Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani (Fujitsu Lab.) CPM2015-136 ICD2015-61 |
This paper describes the impedance reduction technologies in build-up package substrates for high performance CPU, such ... [more] | CPM2015-136 ICD2015-61 pp.51-54 |
| EMCJ, WPT (Joint) |
2015-01-22 12:15 |
Okinawa | Okinawaken Ｊichikaikan | Co-Analysis for SI/PI Problems of Differential Line in Multi-Layer PCB Yuki Kawamitsu, Yoshio Kami (UEC), Kimitoshi Murano (Tokai Univ.), Fengchao Xiao (UEC) EMCJ2014-87 |
Recently, the PCB with multi-layer substrate (Multi-layer PCB) is extensively used with the trend of small size and high... [more] | EMCJ2014-87 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:15 |
Kagoshima | Co-design for reducing power supply noises with On-die PDN Impedance Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86 |
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electro... [more] | CPM2013-109 ICD2013-86 pp.7-12 |
|
| ICD, ITE-IST | 2013-07-05 17:15 |
Hokkaido | San Refre Hakodate | Equivalent circuit representation of silicon substrate coupling of active RF components Naoya Azuma, Makoto Nagata (Kobe univ.) ICD2013-44 |
Substrate coupling of radio frequency (RF) active components is represented by equivalent circuits unifying a resistive ... [more] | ICD2013-44 pp.125-128 |
| EMCJ | 2013-04-12 14:10 |
Okayama | Okayama Univ. | Noise Investigation of Cryptographic ICs for Side-Channel Analysis by Means of Equivalent Current Source Model
-- A Study with SASEBO-G -- Kengo Iokibe, Tetsuo Amano, Yoshitaka Toyota (Okayama Univ.), Tetsushi Watanabe (Industrial Technology Center of Okayama Prefecture) EMCJ2013-5 |
It is an important issue to estimate noise for the side-channel analysis that occur in cryptographic integrated circuits... [more] | EMCJ2013-5 pp.25-30 |
| EMCJ (2nd) |
2012-11-29 15:15 |
Tokyo | NICT | Lossy Resonators for Suppressing Power-bus Resonance of Printed Circuit Board Farhan Zaheed Mahmood, Yoshitaka Toyota, Kengo Iokibe (Okayama Univ.) |
Power-bus resonance of printed circuit boards (PCB) causes propagation of electromagnetic interference (EMI) and detract... [more] | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 10:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A LSI-Package-Board co-evaluation of Power noise in the Digital LSI Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ.) VLD2012-91 DC2012-57 |
Problems related with power noise in LSI system are getting prominent because of the higher integration and lower $V_{d... [more] |
VLD2012-91 DC2012-57 pp.183-188 |
| EMCJ | 2012-04-20 15:35 |
Ishikawa | Kanazawa Univ. | RL Damper Circuit for Electoromagnetic Compatibility and Power Integrity of Integrated Circuits Ryosuke Yamagata, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2012-8 |
Resonances of the parasitic impedance in power distribution network (PDN) increase power current in radio frequency that... [more] | EMCJ2012-8 pp.43-48 |
| EMT, PN, LQE, OPE, MWP, EST, IEE-EMT [detail] | 2012-01-26 09:55 |
Osaka | Osaka Univ. Convention Center | Measurement of IC Package Inductance with Transmission Line Embedded in Package Kengo Iokibe, Ayumi Tanimichi, Yoshitaka Toyota (Okayama Univ.) PN2011-35 OPE2011-151 LQE2011-137 EST2011-85 MWP2011-53 |
It is of importance for designers to possess accurate inductances of IC packages in power integrity (PI) and electromagn... [more] | PN2011-35 OPE2011-151 LQE2011-137 EST2011-85 MWP2011-53 pp.11-16 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:25 |
Miyazaki | NewWelCity Miyazaki | Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ./CREST,JST) CPM2011-163 ICD2011-95 |
Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-p... [more] | CPM2011-163 ICD2011-95 pp.73-78 |
| EMCJ, IEE-EMC | 2011-10-28 13:50 |
Aomori | Hachinohe Grand Hotel | Insertion of Dumping Resistor to Reduce RF IC-Power-Current Peak Caused by Resonance due to Parasitic Impedance Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2011-84 |
High-frequency current caused by simultaneous switching of digital gates which leaks toward the DC power supply into the... [more] | EMCJ2011-84 pp.29-34 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 10:40 |
Fukuoka | Kyushu University | Evaluation of frequency components of power noise in CMOS digital LSI Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) CPM2010-124 ICD2010-83 |
Recent trends of electric devices are higher performance and/or lower power consumption. To achieve these designs, LSI ... [more] |
CPM2010-124 ICD2010-83 pp.1-6 |
| CAS (2nd) |
2010-10-06 11:45 |
Chiba | Makuhari Messe | [Invited Talk]
PI/SI/EMI simulation technology for high-speed electronic design Hideki Asai (Shizuoka Univ.) |
A variety of noise problems, such as signal integrity, power integrity and electromagnetic interference have become very... [more] | |
| ICD, ITE-IST | 2010-07-22 09:30 |
Osaka | Josho Gakuen Osaka Center | On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration Takushi Hashida, Hiroshi Matsumoto, Makoto Nagata (Kobe Univ.) ICD2010-21 |
On-chip waveform capture exhibits the resolution of 10 ps and 200 uV with 1024 steps, and SFDR of 63.2dB in 700-MHz sign... [more] | ICD2010-21 pp.1-4 |
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