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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| EE, WPT, IEE-SPC (Joint) [detail] |
2015-07-06 13:00 |
Kyoto | A programmable power supply array utilizing one chip POL Madoka Higashida, Takayuki Yamamoto, Seiya Abe, Satoshi Matsumoto (KIT)  EE2015-6 |
We propose a full digital control strategy for multiple input and output voltages POLs based on power SoC. We also repor... [more] | EE2015-6 pp.1-6 |
|
| ICD, ITE-IST | 2015-07-03 10:30 |
Kanagawa | National Defense Academy | [Invited Talk]
All-Digital-ADC TAD for Sensor/RF Digitization Resulting in Distinctive Scalability Takamoto Watanabe, Shigenori Yamauchi, Nobuyuki Taguchi, Tomohito Terasawa (DENSO) ICD2015-19 |
Sensor nodes and communications become more and more important factors in IoT applications, including autonomous car sys... [more] | ICD2015-19 pp.27-32 |
| EE | 2015-01-30 10:30 |
Kumamoto | Sakura-No-Baba JOSAIEN | A Control Strategy of a Multi Output POL for Power Supply on Chip Applications Takayuki Yamamoto, Seiya Abe, Satoshi Matsumoto (Kyushu Inst. of Tech.) EE2014-35 |
We propose a full digital control strategy for multiple output POLs based on power SoC. We also report the simulation an... [more] | EE2014-35 pp.37-42 |
| OCS, CS (Joint) |
2015-01-22 15:35 |
Tokushima | Tokushima University | [Special Invited Talk]
Low-power Techniques for Network System on a Chip Satoshi Shigematsu, Naoki Miura, Yuki Arikawa, Namiko Ikeda (NTT) CS2014-83 |
This paper presents examples of low-power circuit schemes for Network SoC and lowering power of network equipment by usi... [more] | CS2014-83 pp.13-18 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] | ICD2014-82 CPSY2014-94 p.43 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:05 |
Oita | B-ConPlaza | Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures Hayate Okuhara, Hideharu Amano (Keio Univ.) RECONF2014-36 |
(To be available after the conference date) [more] | RECONF2014-36 pp.13-18 |
| ICD, SDM | 2014-08-05 15:20 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | CMOS Relaxation Oscillator for a Real-Time Clock Application Keishi Tsubaki, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) SDM2014-80 ICD2014-49 |
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application... [more] | SDM2014-80 ICD2014-49 pp.99-104 |
| ICD, ITE-IST | 2014-07-03 11:15 |
Shimane | Izumo-shi (Shimane) | [Invited Talk]
Extremely Low Power and Low Voltage Sucessive Approximation Register ADC Hiroki Ishikuro (Keio Univ.) ICD2014-22 |
Recently, large number of research results of energy efficient, charge redistribution type, successive approximation reg... [more] | ICD2014-22 pp.17-22 |
| SDM, ICD | 2013-08-02 10:25 |
Ishikawa | Kanazawa University | 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 |
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] | SDM2013-77 ICD2013-59 pp.59-64 |
| DC, CPSY (Joint) |
2013-08-02 17:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Design of Variable Stages Pipeline Processor on Superscalar Processor Tomoyuki Nakabayashi, Seiji Miyoshi, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2013-27 |
This paper designs a high performance and low energy superscalar processor using variable stages pipeline (VSP) techniqu... [more] | CPSY2013-27 pp.103-108 |
| SCE | 2013-07-22 11:15 |
Tokyo | Kikaishinkou-kaikan Bldg. | Evaluation of Energy Dissipation and Bit-Error-Rate of Adiabatic Quantum-Flux-Parametron Logic with Under-Damped Junctions Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2013-13 |
Adiabatic quantum-flux-parametron (AQFP) logic is ultimately energy-efficient. The bit energy and bit-error-rate (BER) o... [more] | SCE2013-13 pp.17-22 |
| EST, MWP, OPE, MW, EMT, IEE-EMT [detail] | 2013-07-18 13:40 |
Hokkaido | Wakkanai Synthesis Cultural Center | The estimation method of power consumption considering traffic characteristics for communications SoCs Ritsu Kusaba, Hiroyuki Uzawa, Tomoaki Kawamura, Kenji Kawai, Yuki Arikawa, Satoshi Shigematsu (NTT) MW2013-52 OPE2013-21 EST2013-16 MWP2013-11 |
We proposed a method for estimating the power consumption of communications SoC. The method consists of three steps. The... [more] | MW2013-52 OPE2013-21 EST2013-16 MWP2013-11 pp.39-44 |
| ICD, ITE-IST | 2013-07-04 10:20 |
Hokkaido | San Refre Hakodate | Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near-Threshold Logic Circuits Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) ICD2013-26 |
In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonan... [more] | ICD2013-26 pp.13-18 |
| DC, CPSY | 2013-04-26 14:15 |
Tokyo | Proposal of Source-code Generator named Simple Logic Compiler for Low Power Accelerator CMA Nobuaki Ozaki, Hideharu Amano (Keio Univ.) CPSY2013-4 DC2013-4 |
We propose Simple Logic Compiler for Low power accelerator named CMA. Simple Logic Compiler receives simple script writt... [more] | CPSY2013-4 DC2013-4 pp.19-24 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 09:10 |
Nagasaki | Guarantee of finising of calculate for a low power accelerator CMA Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuaki Ozaki, Hideharu Amano (Keio Univ.) CPSY2012-86 DC2012-92 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE (Pr... [more] |
CPSY2012-86 DC2012-92 pp.205-210 |
|
| SDM | 2013-02-04 13:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Smart interconnect technology using atom switch for low-power programmable Logic Munehiro Tada, Toshitsugu Sakamoto, Makoto Miyamura, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (LEAP) SDM2012-152 |
Multi-level interconnect technology in ULSI is now facing the difficulty of the scaling limit. “BEOL devices” having a n... [more] | SDM2012-152 pp.9-14 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] | VLD2012-102 DC2012-68 pp.249-254 |
| ICD, SDM | 2012-08-02 13:00 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Lecture]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, The University of Tokyo) SDM2012-68 ICD2012-36 |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation (ULV) CMOS with maximum power efficien... [more] | SDM2012-68 ICD2012-36 pp.29-32 |
| DC, CPSY (Joint) |
2012-08-02 16:15 |
Tottori | Torigin Bunka Kaikan | Co-processor of a low power accelerator CMA Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2012-14 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE(Proc... [more] | CPSY2012-14 pp.31-36 |
| SDM, ED (Workshop) |
2012-06-29 09:45 |
Okinawa | Okinawa Seinen-kaikan | [Invited Talk]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, Univ. of Tokyo) |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation CMOS with maximum power efficiency can... [more] | |
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