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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-23 17:15 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
Preliminary Evaluation of Low Power Optimized ORB-SLAM3 on Jetson Xavier NX Raito Hayashi (Waseda Univ.), Hiroki Mikami, Akira Nodomi (Oscar Tech.), Sadahiro Kimura (NSITEXE,Inc.), Keiji Kimura, Hironori Kasahara (Waseda Univ.)  CPSY2022-40 DC2022-99 |
[more] | CPSY2022-40 DC2022-99 pp.37-42 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-11 09:30 |
Online | Online | LocalMapping Parallelization and CPU Allocation Method on ORB-SLAM3 Kazuki Yamamoto, Takugo Osakabe, Honoka Koike, Tohma Kawasumi, Kazuki Fujita, Toshiaki Kitamura (Waseda Univ.), Akihiro Kawashima, Akira Nodomi (Oscar Tech.), Sadahiro Kimura (NSITEXE,Inc.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2021-58 DC2021-92 |
(To be available after the conference date) [more] | CPSY2021-58 DC2021-92 pp.79-84 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-25 14:40 |
Online | Online | Parallelization and Vectorization of SpMM for Sparse Neural Network Yuta Tadokoro, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2020-55 DC2020-85 |
Pruning is one of the well-known model compression techniques in Deep Learning. Eliminating less important weights in th... [more] | CPSY2020-55 DC2020-85 pp.31-36 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2020-02-28 10:55 |
Kagoshima | Yoron-cho Chuou-Kouminkan | Extension of OSCAR Compiler for Parallelizing C++ Programs Tohma Kawasumi, Tilman Priesner, Masato Noguchi, Jixin Han, Hiroki Mikami (Waseda Univ.), Akihiro Kawashima, Keishiro Tanaka (OscarTechnology Corp.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2019-110 DC2019-116 |
With the increasing focuses on multicore processors, the OSCAR compiler is known as an automatically parallelizing compi... [more] | CPSY2019-110 DC2019-116 pp.151-156 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 10:20 |
Kagoshima | Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2014-178 DC2014-104 |
This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications... [more] | CPSY2014-178 DC2014-104 pp.95-100 |
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| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2014-03-16 14:30 |
Okinawa | A parallelizing compiler cooperative acceleration technique of multicore architecture simulation using a statistical method Gakuho Taguchi, Keiji Kimura, Hironori Kasahara (Waseda Univ.) CPSY2013-117 DC2013-104 |
A parallelizing compiler cooperative acceleration technique for multicore architecture simulation is proposed in this pa... [more] | CPSY2013-117 DC2013-104 pp.289-294 |
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| MSS | 2010-01-21 13:25 |
Aichi | Toyota Central R&D Labs. | Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38 |
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] | CST2009-38 pp.7-12 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 11:15 |
Osaka | Shoushin Kaikan | Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] | ICD2008-140 pp.63-68 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 11:45 |
Osaka | Shoushin Kaikan | Local Memory Management Scheme by a Compiler for Multicore Processor Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] | ICD2008-141 pp.69-74 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 14:45 |
Osaka | Shoushin Kaikan | A Power Saving Scheme on Multicore Processors Using OSCAR API Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
Effective power reduction of an application program on multicore processors requires appropriate power control for each ... [more] | ICD2008-145 pp.93-98 |
| ICD, IPSJ-ARC | 2008-05-13 10:30 |
Tokyo | An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.) |
In order to use a large number of processor cores in a chip, hierarchical coarse grain task parallel processing, which e... [more] | ICD2008-20 pp.19-24 |
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| ICD, IPSJ-ARC | 2008-05-14 13:45 |
Tokyo | Automatic Parallelization of Restricted C Programs using Pointer Analysis Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper describes a restriction on pointer usage in C language for parallelism extraction by an automatic parallelizi... [more] | ICD2008-30 pp.69-74 |
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| ICD, SDM | 2007-08-23 09:20 |
Hokkaido | Kitami Institute of Technology | Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71 |
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] | SDM2007-143 ICD2007-71 pp.11-16 |
| ICD, IPSJ-ARC | 2007-05-31 14:15 |
Kanagawa | A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22 |
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. ... [more] | ICD2007-22 pp.31-35 |
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