IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 109, Number 412

Silicon Device and Materials

Workshop Date : 2010-02-05 / Issue Date : 2010-01-29

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Table of contents

SDM2009-182
[Keynote Address] Key Issues and Future Prospects for 3-D Integration Technology
Mitsumasa Koyanagi, Takafumi Fukushima, Kangwook Lee, Tetsu Tanaka (Tohoku Univ.)
pp. 1 - 6

SDM2009-183
Highly-Reliable Cu Interconnect covered with CoWB Metal-cap in a Waterproof Molecular-Pore-Stack (MPS)-SiOCH film
Yoshihiro Hayashi, Masayoshi Tagami, Naoya Furutake, Naoya Inoue, Emiko Nakazawa, Kouji Arita (NEC Electronics)
pp. 7 - 11

SDM2009-184
Feasibility Study of 70nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation
Naofumi Nakamura, Noriaki Oda, Eiichi Soda, Nobuki Hosoi, Akifumi Gawase, Hajime Aoyama, Y. Tanaka, D. Kawamura, S. Chikaki, M. Shiohara, Nobuaki Tarumi, S. Kondo, Ichiro Mori, S. Saito (SELETE)
pp. 13 - 18

SDM2009-185
Advanced Direct-CMP Process for Porous Low-k Thin Film
Hayato Korogi (Panasonic), Hiroyuki Chibahara (Renesas), S. Suzuki, M. Tsutsue (Panasonic), K. Seo (Panasonic Semiconductor Engineering), Y. Oka, K. Goto, M. Akazaw, Hiroshi Miyatake (Renesas), S. Matsumoto, T. Ueda (Panasonic)
pp. 19 - 23

SDM2009-186
Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9)
M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba)
pp. 25 - 29

SDM2009-187
Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond
Yumi Hayashi, Noriaki Matsunaga, Makoto Wada, Shinichi Nakao, Atsuko Sakata, Kei Watanabe, Hideki Shibata (Toshiba)
pp. 31 - 36

SDM2009-188
Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond
K. Ohmori, K. Mori, K. Maekawa (Renesas), Kazuyuki Kohama, Kazuhiro Ito (Kyoto Univ.), T. Ohnishi, M. Mizuno (KOBE STEEL), K. Asai (Renesas), M. Murakami (Ritsumeikan Trust), Hiroshi Miyatake (Renesas)
pp. 37 - 41

SDM2009-189
Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging
Shintaro Yamamichi, Kentaro Mori, Katsumi Kikuchi, Hideya Murai, D. Ohshima, Y. Nakashima (NEC), Kouji Soejima, Masaya Kawano (NEC Electronics), Tomoo Murakami (NEC)
pp. 43 - 48

SDM2009-190
Defects in Cu/low-k Interconnects Probed Using Monoenergetic Positron Beams
Akira Uedono (Tsukuba Univ.), Naoya Inoue, Y. Hayashi, K. Eguchi, T. Nakamura, Y. Hirose, Masaki Yoshimaru (STARC), Nagayasu Oshima, Toshiyuki Ohdaira, R. Suzuki (National Institute of Advanced Industrial Science and Technology)
pp. 49 - 52

SDM2009-191
Evaluation of Dielectric Constant through Direct CMP of Porous Low-k Film
Masako Kodera, T. Takahashi, G. Mimamihaba (Toshiba Corp.)
pp. 53 - 58

SDM2009-192
Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns
Atsuko Yamaguchi, D. Ryuzaki, Kenichi Takeda (Hitachi), Hiroki Kawada (Hitachi High-Tech.)
pp. 59 - 63

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan