Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2008] | [2009] | [2010] | [2011] | [2012] | [2013] | [2014] | [Japanese] / [English]
CPSY2011-54
Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications
Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 1 - 6
CPSY2011-55
Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register
Keita Manabe, Rika Uegaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 7 - 12
CPSY2011-56
Sound preprocessing circuit by consonant and vowel recognition system
Keita Okamoto, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 13 - 18
CPSY2011-57
Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift
Takatosi Uchizono, Kazuya Osaku, Akinobu Tsuyuki, Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa (TUAT)
pp. 19 - 24
CPSY2011-58
An Image Recognition System with Hierarchical Feature Learning Function
Masahiro Ariizumi, Baku Ogasawara, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 25 - 30
CPSY2011-59
On a Decomposed MTMDDs for CF Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT)
pp. 31 - 36
CPSY2011-60
An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor
Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ)
pp. 37 - 42
CPSY2011-61
Extension of ITRON Specification OS for Multithreaded Processors
Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 43 - 48
CPSY2011-62
Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router
Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.)
pp. 49 - 54
CPSY2011-63
A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique
Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba)
pp. 55 - 60
CPSY2011-64
A bandwidth control scheme based on a traffic analysis for an on-chip router
Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 61 - 66
CPSY2011-65
A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP
Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.)
pp. 67 - 72
CPSY2011-66
Architecture and estimation of reconfigurable processor for multimedia processing
Asuka Hayashi, Shuu'ichirou Yamamoto, Hideo Maejima (Tokyo Tech)
pp. 73 - 76
CPSY2011-67
Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit
Yusaku Yamazaki, Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 77 - 82
CPSY2011-68
A Mobile Robot System using Intelligent Circuit in Silicon
Takuya Suzuki, Yusaku Yamazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 83 - 88
CPSY2011-69
Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation
Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
pp. 89 - 94
CPSY2011-70
High-Level Synthesis of Hardware Relinkable to Software
Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
pp. 95 - 100
CPSY2011-71
The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams
Daiki Kano, Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH)
pp. 101 - 106
CPSY2011-72
Interconnect Reduction in Binding Procedure of HLS
Hao Cong, Song Chen, Takeshi Yoshimura (Waseda Univ.)
pp. 107 - 109
CPSY2011-73
A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set
Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 111 - 116
CPSY2011-74
Error Checker using Binary tree structure of Residue Signed-Digit Additions
Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.)
pp. 117 - 121
CPSY2011-75
Discussion of Performance Prediction Model for Symmetric Block Ciphers on CUDA
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)
pp. 123 - 128
CPSY2011-76
development and evaluation of ParaRuby: a distributed GPGPU framework using Ruby
Ryo Nakamura, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.)
pp. 129 - 134
CPSY2011-77
Implementation and its Evaluation of Distributed PC Grid System
Junji Umemoto, Hiroyuki Ebara, Bunryu U (Kansai Univ.)
pp. 135 - 140
CPSY2011-78
Implementation of Numerical Circuit on 3D FPGA-Array
Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
pp. 141 - 146
CPSY2011-79
Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster
Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.)
pp. 147 - 152
CPSY2011-80
0.18 um process optically reconfigurable gate array VLSI
Takahiro Watanabe, Minoru Watanabe (Shizuoka Univ.)
pp. 153 - 156
CPSY2011-81
Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit
Takashi Yoza, Minoru Watanabe (Shizuoka Univ.)
pp. 157 - 161
CPSY2011-82
Study of pattern area and reconfigurable logic circuit with DG/CNT transistor
Takamichi Hayashi, Shigeyoshi Watanabe (SIT)
pp. 163 - 168
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.