Online edition: ISSN 2432-6380
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VLD2022-19
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM
Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII)
pp. 1 - 6
VLD2022-20
A Study on Co-Optimization of logical structure and bit-line placement for Parallel Prefix Adders
Mineo Kaneko (JAIST)
pp. 7 - 12
VLD2022-21
A Routing Method by SAT for Set-Pair Routing Problem
Koki Nagakura, Rintaro Yokoya, Kunihiro Fujiyoshi (Tokyo Univ of A and T)
pp. 13 - 18
VLD2022-22
A Study of a Design Methodology for Various CGRA based on Diplomacy
Takuya Kojima (UTokyo/JST PRESTO), Makoto Saito, Hiroshi Nakamura (UTokyo)
pp. 19 - 24
VLD2022-23
On reduction of test patterns for a Multiplier Using Approximate Computing
Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ)
pp. 25 - 30
VLD2022-24
A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage
Ruoxi Yu, Kazuteru Namba (Chiba Univ.)
pp. 31 - 36
VLD2022-25
A Don't Care Filling Method of control signals for controllers to Maximize the Number of Distinguishable Hard ware Element Pairs
Yui Otsuka, Yuya Chida, Xu Haofeng, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.)
pp. 37 - 42
VLD2022-26
A Test Generation Merhod Based on Design for Diagnosability at RTL
Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.)
pp. 43 - 48
VLD2022-27
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
pp. 49 - 54
VLD2022-28
FPGA-based Accelerators System with Autonomous DMA Engine
Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki (NTT)
pp. 55 - 60
VLD2022-29
A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.)
pp. 61 - 66
VLD2022-30
(See Japanese page.)
pp. 67 - 71
VLD2022-31
Method of Halved Interaction Elements with Regularity Arrangement that achieves Independent Double Systems for Scalable Fully Coupled Annealing Processing
Shinjiro Kitahara, Akari Endo, Taichi Megumi, Takayuki Kawahara (TUS)
pp. 72 - 77
VLD2022-32
Evaluating system level security of cryptography module
Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuji Miki, Makoto Nagata (Kobe Univ.)
pp. 78 - 81
VLD2022-33
Evaluation of power delivery networks in secure semiconductor systems
Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.)
pp. 82 - 86
VLD2022-34
NA
Tomokazu Yoshimura, Shirai Tatsuhiko, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
pp. 87 - 92
VLD2022-35
N/A
Soma Kawakami (Waseda Univ.), Dema Ba, Kentaro Ohno, Satoshi Yagi, Junji Teramoto (NTT), Nozomu Togawa (Waseda Univ.)
pp. 93 - 98
VLD2022-36
N/A
Keisuke Fukada (Waseda Univ.), Matthieu Parizy (Waseda Univ./Fujitsu LTD.), Yoshinori Tomita (Fujitsu LTD.), Nozomu Togawa (Waseda Univ.)
pp. 99 - 104
VLD2022-37
N/A
Yuta Yachi, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
pp. 105 - 110
VLD2022-38
Development of 65nm-Cryo-CMOS Circuit Design Library
Toshitsugu Sakamoto, Makoto Miyamura, Kazunori Funahashi, Koichiro Okamoto, Munehiro Tada (NBS), Takahisa Tanaka, Ken Uchida (Tokyo Univ.), Hiroki Ishikuro (Keio Univ.)
pp. 111 - 114
VLD2022-39
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops
Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.)
pp. 115 - 120
VLD2022-40
A fast SRAF optimization used LUT based point intensity calculation
Sota Saito, Atsushi Takahashi (Tokyo Tech)
pp. 121 - 126
VLD2022-41
Mask Optimization Using Voronoi Partition and Iterative Improvement
Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA)
pp. 127 - 132
VLD2022-42
A contact angle estimation method using two coplanar capacitive sensors of different sizes
Tsubasa Furuta, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (USP)
pp. 133 - 137
VLD2022-43
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise
Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo)
pp. 138 - 143
VLD2022-44
Deep Learning-based Hierarchical Object Detection System for High-Resolution Images
Yusei Horikawa, Makoto Sugaya, Renpei Yoshida, Kazuma Mashiko, Tetsuya Matsumura (Nihon Univ.)
pp. 144 - 149
VLD2022-45
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter
Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.)
pp. 150 - 155
VLD2022-46
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects
Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 156 - 161
VLD2022-47
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC
Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 162 - 167
VLD2022-48
FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme
Hisashi Okamoto, Jun Ma, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ), Akihiro Shimizu (Kochi Univ. of Technology)
pp. 168 - 173
VLD2022-49
Design and Trial Production of Stochastic Resonance Processor using Differential Input Buffer in FPGA
Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa (Tokyo Denki Univ.)
pp. 174 - 177
VLD2022-50
(See Japanese page.)
pp. 178 - 181
VLD2022-51
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples
Yuta Fukuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.)
pp. 182 - 187
VLD2022-52
Implementation of stereo matching with Kria SOM toward precise field crop height measurement
Ryo Nakagawa, Yoshiki Yamaguchi (Univ. of Tsukuba), Iman Firmansyah (BRIN)
pp. 188 - 193
VLD2022-53
FPGA Implementation of Learned Image Compression
Heming Sun (Waseda U), Qingyang Yi (UTokyo), Jiro Katto (Waseda U), Masahiro Fujita (UTokyo)
pp. 194 - 199
VLD2022-54
NA
Kota Hisafuru, Nozomu Togawa (Waseda Univ.)
pp. 200 - 205
VLD2022-55
Error detection and countermeasures caused by hardware trojan inserted computers
Takuro Kasai, Masashi Imai (Hirosaki Univ.)
pp. 206 - 211
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.