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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 14:30 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing Kenta Suzuki, Keizo Hiraga, Bessho Kazuhiro (Sony), Kimiyoshi Usami (SIT), Taku Umebayashi (Sony)  ICD2024-7 |
(To be available after the conference date) [more] | ICD2024-7 pp.20-23 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 09:55 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
MTJ-PUF with Input Decoder and Evaluation of Machine Learning Resistance Takumi Kikuchi, Kimiyoshi Usami (SIT) VLD2023-44 ICD2023-52 DC2023-51 RECONF2023-47 |
Physically Unclonable Function (PUF), one of the LSI individual authentication techniques, is vulnerable to machine lear... [more] | VLD2023-44 ICD2023-52 DC2023-51 RECONF2023-47 pp.82-87 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 10:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control Kousei Kaizu, Kimiyoshi Usami (SIT) VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 |
Non-Volatile Flip Flops (NVFF) using Magnetic Tunnel Junction (MTJ) enable non-volatile power gating and reduce leakage ... [more] | VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 pp.88-93 |
| ICD | 2023-04-11 16:05 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Keynote Address]
Game Change by Spintronics Low Power semiconductors and its contribution to a carbon-neutral society
-- from STT/SOT-MRAM to its application to IoT/AI processors -- Tetsuo Endoh (Tohoku Univ.) ICD2023-13 |
[more] | ICD2023-13 p.30 |
| SDM | 2023-01-30 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. B3-1 | [Invited Talk]
25 nm iPMA-type Hexa-MTJ with solder reflow capability and endurance >107 for eFlash-type MRAM H Honjoi, K Nishioka, S Miura, Hiroshi Naganuma, T Watanabe, T Nasuno, T Tanigawa, Y Noguchi, H Inoue, M Yasuhiro, S Ikeda, T Endoh (Tohoku Univ.) SDM2022-81 |
A solder reflow capable eflash-type MRAM was realized by interfacial perpendicular magnetic anisotropy Hexa-CoFeB/MgO-in... [more] | SDM2022-81 pp.9-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 09:55 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.) VLD2022-39 ICD2022-56 DC2022-55 RECONF2022-62 |
LSI has been developed by miniaturization, but the increase in leakage power caused by it has become a problem. Non-vola... [more] | VLD2022-39 ICD2022-56 DC2022-55 RECONF2022-62 pp.115-120 |
| VLD, HWS [detail] | 2022-03-07 14:30 |
Online | Online | MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-86 HWS2021-63 |
Non-volatile memory (NVM) using magnetic tunnel junction (MTJ) devices can prevent the increase in leakage current, whic... [more] | VLD2021-86 HWS2021-63 pp.51-56 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:10 |
Online | Online | MTJ-based non-volatile SRAM circuit with data-aware store control for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 |
In recent years, the increase of leakage power in LSIs has become a problem, and one of the methods to reduce the leakag... [more] | VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 pp.13-18 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 14:00 |
Online | Online | Physically Unclonable Functions(PUF) curcuit using Non-Volatile Flip-Flop and security evaluation against modeling attacks Hiroki Ishihara, Kimiyoshi Usami (Shibaura IT) VLD2020-37 ICD2020-57 DC2020-57 RECONF2020-56 |
In recent years, imitative LSIs have become a serious problem and security technology PUF to use manufacturing variabili... [more] | VLD2020-37 ICD2020-57 DC2020-57 RECONF2020-56 pp.139-144 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 14:25 |
Online | Online | Energy Efficient Approximate Storing of Image Data for Non-volatile Memory Yoshinori Ono, Kimiyoshi Usami (SIT) VLD2020-38 ICD2020-58 DC2020-58 RECONF2020-57 |
A non-volatile memory (NVM) employing MTJ has a lot of strong points. However, it consumes a lot of energy when writing ... [more] | VLD2020-38 ICD2020-58 DC2020-58 RECONF2020-57 pp.145-150 |
| HWS, VLD [detail] | 2020-03-04 13:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
MTJ-based Nonvolatile Flip-Flop Circuit Using Dual Power Supplies for Low-voltage Operation Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2019-99 HWS2019-72 |
One of the leakage reduction techniques is nonvolatile power gating(NVPG) by using magnetic tunnel junction(MTJ). In the... [more] | VLD2019-99 HWS2019-72 pp.31-36 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 11:00 |
Hiroshima | Satellite Campus Hiroshima | [Keynote Address]
Challenge of Post CMOS Circuit Technologies for AI Hardware Takahiro Hanyu (Tohoku Univ.) |
Recently, it is impartant that the impact of artificial intelligence (AI) is being widely understood in several applicat... [more] | |
| RECONF | 2018-05-25 10:35 |
Tokyo | GATE CITY OHSAKI | Design of an MTJ-Based Multi-Functional Lookup Table Circuit Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu (Tohoku Univ.) RECONF2018-12 |
A multi-functional nonvolatile lookup table (LUT) circuit is described using a magnetic tunnel junction (MTJ) and CMOS h... [more] | RECONF2018-12 pp.59-64 |
| VLD, IPSJ-SLDM | 2018-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2018-2 |
In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is... [more] | VLD2018-2 pp.19-24 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| ICD | 2017-04-20 10:35 |
Tokyo | [Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.) ICD2017-2 |
[more] | ICD2017-2 pp.5-9 |
|
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| SDM | 2017-01-30 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 |
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] | SDM2016-135 pp.21-24 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Line selection to reduce store-energy in MTJ-based non-volatile caches Takamasa Fukasawa, Kimiyoshi Usami (SIT) CAS2016-18 VLD2016-24 SIP2016-52 MSS2016-18 |
There is a technique of power gating for reducing the energy consumption of the cache. The technique is a combination of... [more] | CAS2016-18 VLD2016-24 SIP2016-52 MSS2016-18 pp.97-102 |
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