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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2021-01-28 14:05 |
Online | Online | [Invited Talk]
Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance Kazuki Monta (Kobe Univ.)  SDM2020-51 |
In semiconductor integrated circuits, power signal integrity(PSI) and electromagnetic compatibility caused by power supp... [more] | SDM2020-51 pp.8-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | [Invited Talk]
Development of Via Structures in IC Package Substrates for Impedance Reduction Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani (Fujitsu Lab.) CPM2015-136 ICD2015-61 |
This paper describes the impedance reduction technologies in build-up package substrates for high performance CPU, such ... [more] | CPM2015-136 ICD2015-61 pp.51-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:15 |
Kagoshima | Co-design for reducing power supply noises with On-die PDN Impedance Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.) CPM2013-109 ICD2013-86 |
Power integrity is a serious issue in CMOS LSI systems, because power supply noise induces logic instability and electro... [more] | CPM2013-109 ICD2013-86 pp.7-12 |
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| EMCJ | 2012-04-20 15:35 |
Ishikawa | Kanazawa Univ. | RL Damper Circuit for Electoromagnetic Compatibility and Power Integrity of Integrated Circuits Ryosuke Yamagata, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2012-8 |
Resonances of the parasitic impedance in power distribution network (PDN) increase power current in radio frequency that... [more] | EMCJ2012-8 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:25 |
Miyazaki | NewWelCity Miyazaki | Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ./CREST,JST) CPM2011-163 ICD2011-95 |
Power noise of an integrated circuit (IC) chip is dominantly characterized by the frequency-domain impedance of a chip-p... [more] | CPM2011-163 ICD2011-95 pp.73-78 |
| EMCJ, IEE-EMC | 2011-10-28 13:50 |
Aomori | Hachinohe Grand Hotel | Insertion of Dumping Resistor to Reduce RF IC-Power-Current Peak Caused by Resonance due to Parasitic Impedance Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2011-84 |
High-frequency current caused by simultaneous switching of digital gates which leaks toward the DC power supply into the... [more] | EMCJ2011-84 pp.29-34 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 10:40 |
Fukuoka | Kyushu University | Evaluation of frequency components of power noise in CMOS digital LSI Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST) CPM2010-124 ICD2010-83 |
Recent trends of electric devices are higher performance and/or lower power consumption. To achieve these designs, LSI ... [more] |
CPM2010-124 ICD2010-83 pp.1-6 |
| ICD, ITE-IST | 2010-07-22 09:30 |
Osaka | Josho Gakuen Osaka Center | On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration Takushi Hashida, Hiroshi Matsumoto, Makoto Nagata (Kobe Univ.) ICD2010-21 |
On-chip waveform capture exhibits the resolution of 10 ps and 200 uV with 1024 steps, and SFDR of 63.2dB in 700-MHz sign... [more] | ICD2010-21 pp.1-4 |
| EMCJ | 2009-11-20 13:55 |
Tokyo | Aoyama Gakuin Univ. (Aoyama Campus) | Measurement Techniques for On-chip Power Supply Noise Waveforms based on Delay Observation in Inverter Chain Circuits Yutaka Uematsu, Hideki Osaka, Eiichi Suzuki, Masayoshi Yagyu, Tatsuya Saito (Hitachi Co Ltd.) EMCJ2009-83 |
To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measu... [more] |
EMCJ2009-83 pp.25-30 |
| EMCJ | 2008-12-19 11:15 |
Gifu | Gifu Univ. | Compatibility Design of EMI Reduction and Power Integrity by Power Decoupling and Destributed Locating of Capacitors in LSI Power Distribution Network Hiroshi Tanaka, Osami Wada, Takashi Hisakado (Kyoto Univ.) EMCJ2008-91 |
Conventionally a strategy of reducing impedance of DC power distribution network (PDN) for LSI has been adopted to impro... [more] | EMCJ2008-91 pp.31-36 |
| VLD, IPSJ-SLDM | 2008-05-09 10:00 |
Hyogo | Kobe Univ. | [Invited Talk]
NoizeProblems in LSI Design:Challenges and Approaches Makoto Nagata (Kobe Univ.) |
Digital designs intending high-speed and low-power consumption necessarily deal with dynamic power supply noise, for suc... [more] | VLD2008-7 pp.1-6 |
| CPM, ICD | 2008-01-17 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Design of an On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) CPM2007-132 ICD2007-143 |
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The ... [more] | CPM2007-132 ICD2007-143 pp.23-27 |
| CPM, ICD | 2008-01-18 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Tutorial Lecture]
Survey of Analysis Techniques for On-chip Power Distribution Networks Takashi Sato (Tokyo Tech.) CPM2007-140 ICD2007-151 |
Primary techniques and recent trends in power distribution network (PDN) analysis are reviewed in this paper. Quality ... [more] |
CPM2007-140 ICD2007-151 pp.71-76 |
| ICD, SDM | 2007-08-24 08:55 |
Hokkaido | Kitami Institute of Technology | Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variation in SoCs Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura (Kobe Univ.), Rei Akiyama (Renesas Design), Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata (Renesas Technology), Makoto Nagata (Kobe Univ.) SDM2007-156 ICD2007-84 |
Fine-grained built-in probing circuits are distributed at 120 locations on the SoC to allow continuous-time monitoring o... [more] | SDM2007-156 ICD2007-84 pp.85-90 |
| ICD, SDM | 2007-08-24 09:20 |
Hokkaido | Kitami Institute of Technology | An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) SDM2007-157 ICD2007-85 |
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The ... [more] | SDM2007-157 ICD2007-85 pp.91-94 |
| ICD, VLD | 2007-03-07 17:00 |
Okinawa | Mielparque Okinawa | On-chip monitoring for sub-100-nm digital signal integrity Yoji Bando, Koichiro Noguchi, Makoto Nagata (Kobe Univ.) |
A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device ... [more] | VLD2006-116 ICD2006-207 pp.61-66 |
| ICD, CPM | 2007-01-18 10:15 |
Tokyo | Kika-Shinko-Kaikan Bldg. | Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. Tech.), Takao Onoye (Osaka Univ.) |
Power integrity is an crucial design issue in nano-meter technologies because of lowered supply voltage and current incr... [more] | CPM2006-132 ICD2006-174 pp.19-23 |
| ICD, CPM | 2007-01-18 10:55 |
Tokyo | Kika-Shinko-Kaikan Bldg. | Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) |
Delay variability due to dynamic power supply noise is elucidated by on-chip signal waveform measurements at 100-ps/100-... [more] | CPM2006-133 ICD2006-175 pp.25-29 |
| EMCJ | 2006-12-15 10:30 |
Aichi | Nagoya Institute of Technology | EMI Model improvement taking LSI package structure into consideration Takahiro Tsuda, Takanori Uno, Kouji Ichikawa (DENSO) EMCJ2006-84 |
An LSI EMI model was used to analyze conducted emission noise in a PCB. This model has been problem that the accuracy o... [more] | EMCJ2006-84 pp.19-24 |
| EE | 2004-11-04 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Influence of Switching Power Supply Noise on Signal Integrity under CMOS-IC Load Ken-ichi Nishijima (Hakko Electronics), Toshiro Sato, Kiyohito Yamasawa (Shinshu Univ.) |
This paper describes the experimental study on the conduction noise of switching power supply under CMOS-IC load. When t... [more] | EE2004-39 pp.19-24 |
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