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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD | 2024-01-30 13:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)  VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] | VLD2023-94 RECONF2023-97 pp.81-86 |
| NS | 2022-10-06 09:15 |
Hokkaido | Hokkaidou University + Online (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A Communication Timing Schedule Method for FA Network with PLC Program Analysis Daisuke Osagawa, Tomotaka Ogawa, Daisuke Takita (Mitsubishi Electric Corp.) NS2022-89 |
The Factory Automation network has a multiple communication cycles function that reduces the frequency of control commun... [more] | NS2022-89 pp.39-59 |
| ED | 2022-04-21 11:20 |
Online | Online | A High Process Portability All Digital Time domain A/D Converter Takahiro Amada, Cong-Kha Pham (UEC Tokyo) ED2022-6 |
An all digital time domain A/D converter that can be largely synthesized has been proposed. The proposed circuit was des... [more] | ED2022-6 pp.19-22 |
| SS, MSS | 2022-01-12 10:05 |
Nagasaki | Nagasakiken-Kensetsu-Sogo-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Multitask Scheduling for Reducing Total Memory Consumption while Satisfying Deadlines using Adaptive Control according to Dynamic Change of Task Memory Consumption Ryosuke Arai, Akio Nakata (Hiroshima City Univ) MSS2021-48 SS2021-35 |
The authors have previously proposed a multi-task scheduling method LMCLF, which can reduce the total memory usage of th... [more] | MSS2021-48 SS2021-35 pp.95-99 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| DC, CPSY, IPSJ-ARC [detail] | 2020-10-12 10:15 |
Online | Online | Replay overhead reduction in Embedded Non-stop OS that using Trace Buffer Nao Sugiyama, Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.) CPSY2020-17 DC2020-17 |
In an embedded system environment, it is necessary to keep safe the system from some problem. In particular, power suppl... [more] | CPSY2020-17 DC2020-17 pp.1-6 |
| MW, EST, OPE, MWP, EMT, IEE-EMT, THz [detail] | 2019-07-18 13:40 |
Hokkaido | Hakodate City Central Library | Design and Evaluation of 3-Dimensional Printed Reflector Fresnel Lens Antenna Based on Acrylonitrile Butadiene Styrene Plastics for W-Band Millimeter-Wave Radar Applications Shunichi Futatsumori, Nobuhiro Sakamoto, Tomio Soga (ENRI) EMT2019-13 MW2019-26 OPE2019-17 EST2019-15 MWP2019-13 |
This report discusses the design and evaluation of 3-dimensional (3D) printed reflector Fresnel lens antenna based on Ac... [more] | EMT2019-13 MW2019-26 OPE2019-17 EST2019-15 MWP2019-13 pp.41-45 |
| ICD, CPSY, CAS | 2018-12-23 09:30 |
Okinawa | [Poster Presentation]
Digital Reduction of Third-Order Distortions in Time-Interleaved A/D Converters Keisuke Miyakoshi, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-106 ICD2018-90 CPSY2018-72 |
Harmonic distortions appear at the output of an A/D converter (ADC) due to its nonlinearity, degrading the spurious-free... [more] | CAS2018-106 ICD2018-90 CPSY2018-72 pp.107-108 |
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| EST | 2018-09-07 10:20 |
Okinawa | Kumejima-machi, Okinawa | Numerical Analysis of 3-Dimensional Printed Reflector-Lens Antenna Based on Acrylonitrile Butadiene Styrene Plastics for W-Band Millimeter-Wave Radar Applications Shunichi Futatsumori, Nobuhiro Sakamoto (ENRI) EST2018-54 |
This report discusses the numerical analysis of 3-dimensional (3D) printed reflector-lens antenna based on Acrylonitrile... [more] | EST2018-54 pp.63-67 |
| EMCJ, MICT (Joint) |
2018-03-16 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High frequency decoupling for reduction of common-mode current of three-phase inverter Shiki Fujii (Kyoto Univ.), Tohlu Matsushima (Kyutech), Takashi Hisakado, Osami Wada (Kyoto Univ.) EMCJ2017-111 |
Recently, electric vehicles have been developed rapidly, and three-phase inverters are also used in its motor drive circ... [more] | EMCJ2017-111 pp.37-42 |
| PN | 2018-03-06 14:15 |
Kagoshima | Minami Tanemachi Shoko Kaikan | Fast finding method of optical circuit sharing rack groups in the HOLST datacenter network based on time division multiplexing using high-speed optical switches Masayuki Hirono, Akira Yamashita, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2017-111 |
Recently, the energy consumption in data centers is increasing. The authors are working on the research and development... [more] |
PN2017-111 pp.131-136 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Proposal of high precision skew adjustment method with an on-chip setup time measurement circuit Naoto Kamba, Masaki Ishii, Masahiro Sasaki (SIT) CAS2017-84 ICD2017-72 CPSY2017-81 |
In recent years, clock skew which can be tolerated is reduced because the operating speed of integrated circuits increas... [more] | CAS2017-84 ICD2017-72 CPSY2017-81 p.97 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Accelerated Transient Analysis of Power MOSFETs by the Matrix Exponential Method Tatsuya Kamei, Shigetaka Kumashiro, Kazutoshi Kobayashi (KIT) CAS2017-87 ICD2017-75 CPSY2017-84 |
In designing and developing power devices, reduction of simulation time is required. In this study, an accurate metric f... [more] | CAS2017-87 ICD2017-75 CPSY2017-84 pp.107-112 |
| WIT | 2017-08-28 15:45 |
Akita | Faculty of Engineering Science, Akita Univ. | A study of quantitative evaluation and survey of captions and subtitles for older persons and the deaf and hard-of-hearing Yuki Harada, Junji Ohyama (AIST) WIT2017-18 |
(To be available after the conference date) [more] | WIT2017-18 pp.21-26 |
| WIT | 2017-08-29 11:50 |
Akita | Faculty of Engineering Science, Akita Univ. | Design Sommelier : Integrated personalization design technology to reduce the workload of service providers and end users Junji Ohyama (AIST) WIT2017-26 |
(To be available after the conference date) [more] | WIT2017-26 pp.67-72 |
| PN | 2016-11-18 10:00 |
Saitama | KDDI Research, Inc. | HOLST:Architecture design of energy-efficient datacenter network based on ultra high-speed optical switch Masayuki Hirono, Takehiro Sato, Jun Matsumoto, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2016-35 |
Recently, the energy consumption in data centers is increasing. Introducing optical circuit to the inter-rack communica... [more] |
PN2016-35 pp.59-65 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
| DC | 2013-06-21 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10 |
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] | DC2013-10 pp.1-6 |
| VLD | 2010-03-12 10:25 |
Okinawa | Performance evaluation of ADDER with Error-Detection-Correction Mechanism Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ) VLD2009-121 |
In complete-synchronous framework that is adopted as de facto standard in clock-synchronous circuit design, the maximum ... [more] | VLD2009-121 pp.133-137 |
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