IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 22  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2018-08-09
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 Study of Impact of BTI's Local Layout Effect Including Recovery Effect on Various Standard-Cells in 10nm FinFET
Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii (Renesas) SDM2018-47 ICD2018-34
 [more] SDM2018-47 ICD2018-34
(Joint) [detail]
Hiroshima Miyajima-Morino-Yado(Hiroshima) A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98
SDM 2016-01-28
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes
Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125
 [more] SDM2015-125
SDM, ICD 2015-08-24
Kumamoto Kumamoto City Area and Performance Study of FinFET with Detailed Parasitic Capacitance Analysis in 16nm Process Node
Takeshi Okagaki, Koji Shibutani, Masao Morimoto, Yasumasa Tsukamoto, Koji Nii, Kazunori Onozawa (REL) SDM2015-64 ICD2015-33
 [more] SDM2015-64 ICD2015-33
ICD 2015-04-16
Nagano   [Invited Lecture] 20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists
Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii (Renesas) ICD2015-1
 [more] ICD2015-1
ICD 2015-04-16
Nagano   [Invited Lecture] A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline
Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2
 [more] ICD2015-2
SDM 2015-01-27
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist
Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Miki Tanaka, Koji Nii (Renesas) SDM2014-144
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Tes... [more] SDM2014-144
SDM, ICD 2013-08-02
Ishikawa Kanazawa University A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58
 [more] SDM2013-76 ICD2013-58
SDM, ICD 2013-08-02
Ishikawa Kanazawa University 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] SDM2013-77 ICD2013-59
ICD 2013-04-12
Ibaraki Advanced Industrial Science and Technology (AIST) [Invited Lecture] Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics) ICD2013-21
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has two low-vo... [more] ICD2013-21
ICD 2012-12-18
Tokyo Tokyo Tech Front A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM
Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii (Renesas) ICD2012-114
 [more] ICD2012-114
ICD 2012-04-24
Iwate Seion-so, Tsunagi Hot Spring (Iwate) [Invited Talk] Write-/Read- Disturb Issues and Circuit Solutions
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] ICD2012-11
SDM, ICD 2011-08-26
Toyama Toyama kenminkaikan A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs
Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) SDM2011-93 ICD2011-61
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design ... [more] SDM2011-93 ICD2011-61
ICD 2010-04-22
Kanagawa Shonan Institute of Tech. [Invited Talk] Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies -- A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias --
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara (Renesas Electronics) ICD2010-2
We investigate 0.5V 6T-SRAM with asymmetric MOSFET, which contributes to enhance the read and write margin. We also intr... [more] ICD2010-2
ICD 2010-04-22
Kanagawa Shonan Institute of Tech. A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] ICD2010-3
SDM [detail] 2008-11-14
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] [Invited]Robust Design of Embedded SRAM on Deep-submicron Technology
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] SDM2008-178
ICD, SDM 2008-07-17
Tokyo Kikai-Shinko-Kaikan Bldg. A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] SDM2008-131 ICD2008-41
ICD, SDM 2007-08-24
Hokkaido Kitami Institute of Technology A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] SDM2007-168 ICD2007-96
ICD 2007-04-13
Oita   [Invited Talk] A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] ICD2007-11
ICD, SDM 2006-08-18
Hokkaido Hokkaido University A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC
Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology)
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] SDM2006-148 ICD2006-102
 Results 1 - 20 of 22  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan