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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 52  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD 2023-03-03
15:45
Okinawa
(Primary: On-site, Secondary: Online)
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA
Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2022-111 HWS2022-82
We studied the implementation method of PUF for generating a unique ID on FPGA. We adopted a method of controlling the p... [more] VLD2022-111 HWS2022-82
pp.209-214
RECONF 2021-06-08
13:00
Online Online [Invited Talk] Basics, Applications, and International Standardization of Physically Unclonable Functions (PUFs)
Yohei Hori (AIST) RECONF2021-1
A Physically Unclonable Function (PUF) is a security primitive that generates chip-specific values by exploiting device ... [more] RECONF2021-1
p.1
ICD, HWS [detail] 2020-10-26
14:55
Online Online Physical-Level Detection Approach against Hardware Trojans inside Semiconductor Chips (II)
Hirofumi Sakane, Shinichi Kawamura, Kentaro Imafuku, Yohei Hori, Makoto Nagata, Yuichi Hayashi, Tsutomu Matsumoto (AIST) HWS2020-35 ICD2020-24
Hardware Trojans, known to be designed and crafted with malicious intent and deployed to be part of the hardware of the ... [more] HWS2020-35 ICD2020-24
pp.59-64
HWS, VLD [detail] 2020-03-07
10:30
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Causes of Entropy Loss on Non-IID PUFs and their Entropy Estimations (1)
Mitsuru Shiozaki (Ritsumeikan Univ.), Yohei Hori (AIST), Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2019-138 HWS2019-111
Recently, evaluation items and evaluation schemes of Physically Unclonable Functions (PUFs) are discussed in internation... [more] VLD2019-138 HWS2019-111
pp.257-262
HWS, VLD [detail] 2020-03-07
10:55
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Causes of Entropy Loss on Non-IID PUFs and their Entropy Estimations (2)
Mitsuru Shiozaki (Ritsumeikan Univ.), Yohei Hori (AIST), Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2019-139 HWS2019-112
Recently, evaluation items and evaluation schemes of Physically Unclonable Functions (PUFs) are discussed in internation... [more] VLD2019-139 HWS2019-112
pp.263-268
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
09:15
Ehime Ehime Prefecture Gender Equality Center A Study on Dependence between Performance Metrics of PUFs and the Number of Response Bits using PUF Numerical Model
Tatsuya Oyama, Masayoshi Shirahata, Mitsuru Shiozaki, Shunsuke Okura (Ritsumeikan Univ.), Yohei Hori (AIST), Takeshi Fujino (Ritsumeikan Univ.) ICD2019-33 IE2019-39
Recently, performance metrics of Physically Unclonable Function (PUF) are discussed toward international standardization... [more] ICD2019-33 IE2019-39
pp.25-30
HWS, ICD [detail] 2019-11-01
16:50
Osaka DNP Namba SS Bld. Physical-level detection approach against hardware Trojans inside semiconductor chips (I)
Shinichi Kawamura, Kentaro Imafuku, Hirofumi Sakane, Yohei Hori (AIST), Makoto Nagata (AIST/Kobe Univ.), Yuichi Hayashi (AIST/NAIST), Tsutomu Matsumoto (AIST/YNU) HWS2019-65 ICD2019-26
It is of great concern that malicious hardware should be inserted inside semiconductor chips and on printed circuit boar... [more] HWS2019-65 ICD2019-26
pp.47-52
HWS 2019-04-12
15:05
Miyagi Tohoku University Implementation and Experimental Evaluation of Physically Unclonable Functions in 180nm CMOS Process
Mitsuru Shiozaki, Takaya Kubota, Masayoshi Shirahata (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.) HWS2019-4
Evaluation items and evaluation schemes of Physically Unclonable Function (PUF) are discussed in international standardi... [more] HWS2019-4
pp.19-24
HWS, VLD 2019-03-01
15:45
Okinawa Okinawa Ken Seinen Kaikan On Machine Learning Attack Tolerance for PUF-based Device Authentication System
Tomoki Iizuka (UTokyo), Yasuhiro Ogasahara, Toshihiro Katashita, Yohei Hori (AIST), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) VLD2018-133 HWS2018-96
Double-Arbiter PUF (DAPUF) and PL-PUF are known to be highly resistant to machine learning attacks.
In this paper, we p... [more]
VLD2018-133 HWS2018-96
pp.237-242
US 2018-12-10
14:20
Tokyo   Control of the surface profile of thixotropic fluid using ultrasound
Kentaro Masuda, Kyohei Horie, Daisuke Koyama, Mami Matsukawa (Doshisha Univ.) US2018-72
 [more] US2018-72
pp.11-14
VLD, HWS
(Joint)
2018-03-02
14:05
Okinawa Okinawa Seinen Kaikan PL-PUF Implementation by Improvement of Capturing Timing Control Circuit
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike (AIST) VLD2017-126
In this study, we demonstrate the first implementation of a pseudo linear feedback shift register physical unclonable fu... [more] VLD2017-126
pp.225-229
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
11:20
Osaka Ritsumeikan University, Osaka Ibaraki Campus Preliminary experimental platform for FlexPower FPGA evaluation
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike (AIST) RECONF2016-47
 [more] RECONF2016-47
pp.41-46
OME 2016-10-28
17:00
Tokyo Kikai-Shinko-Kaikan Bldg. Stability of organic physically unclonable function for voltage fractuation.
Kazunori Kuribara, Yohei Hori, Toshihiro Katashita (AIST), Kazuaki Kakita, Yasuhiro Tanaka (Ube Inds.), Manabu Yoshida (AIST) OME2016-47
We have investigated stability of novel security system. We fabricate organic ring oscillators (ROs) and consider them a... [more] OME2016-47
pp.39-42
ICD, SDM, ITE-IST [detail] 2016-08-03
09:00
Osaka Central Electric Club [Invited Talk] SRAM PUF using Polycrystalline Silicon Channel FinFET and Its Evaluation
Shin-ichi O'uchi, Yungxun Liu, Yohei Hori, Toshifumi Irisawa, Hiroshi Fuketa, Yukinori Morita, Shinji Migita, Takahiro Mori, Tadashi Nakagawa, Junichi Tsukada, Hanpei Koike, Meishoku Masahara, Takashi Matsukawa (AIST) SDM2016-60 ICD2016-28
 [more] SDM2016-60 ICD2016-28
pp.83-87
RECONF 2015-06-20
11:10
Kyoto Kyoto University A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST) RECONF2015-18
In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verif... [more] RECONF2015-18
pp.97-102
RECONF 2015-06-20
11:35
Kyoto Kyoto University FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3
Yohei Hori, Toshihiro Katashita (AIST) RECONF2015-19
We implemented a key generation circuit using a Physically Unclonable Function (PUF) and Fuzzy Extractor (FE) to a Kinte... [more] RECONF2015-19
pp.103-108
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
08:55
Kagoshima   Improvements and evaluation of bias circuit control for CMOS analog circuit
Ryohei Hori (Ritsumeikan Univ.), Toshio Kumamoto (OSU), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) CPSY2014-175 DC2014-101
The power control using Noff (Normally-off) scheme for realization low power sensor node device is gathering a lot of at... [more] CPSY2014-175 DC2014-101
pp.77-82
ICD, IPSJ-ARC 2015-01-29
15:15
Kanagawa   A study on Normally-OFF Scheme for CMOS Analog Circuit
Ryohei Hori (Ritsumeikan Univ.), Toshio Kumamoto (OSU), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) ICD2014-112
 [more] ICD2014-112
pp.13-18
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
11:10
Kanagawa Hiyoshi Campus, Keio University The proposal of the convex area maze router on LSI design automation
Yohei Horino, Jun Hirayama, Yukiko Ohishi, Toshiyuki Tsutsumi (Meiji Univ.) VLD2014-138 CPSY2014-147 RECONF2014-71
We developed the convex area maze router that extends the channel intersection maze router as a high-speed routing algor... [more] VLD2014-138 CPSY2014-147 RECONF2014-71
pp.163-168
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-27
14:05
Kagoshima   Improved via programmable structured ASIC VPEX3S -- Improvement of basic logic element to improve operation speed --
Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-70 DC2013-36
We have been studying via programmable structured ASIC architecture “VPEX3(Via Programmable Logic using Exclusive-OR Arr... [more] VLD2013-70 DC2013-36
pp.75-80
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