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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 13:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Test Generation for Alleviating Over-testing of Approximate Multipliers Qilin Wang, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  DC2023-97 |
In this study, we discuss the alleviation of over-testing for approximate circuits. We target a design of approximate mu... [more] | DC2023-97 pp.17-22 |
| DC | 2023-12-08 13:50 |
Nagasaki | ARKAS SASEBO (Primary: On-site, Secondary: Online) |
A Multiple Target Seed Generation Method for Random Pattern Resistant Faults Using a Compatible Fault Set on Built-in Self Test Takanobu Sone, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) DC2023-88 |
In recent years, with high density of very large-scale integrated circuits, it has become impractical to store a large n... [more] | DC2023-88 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 16:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 |
Recently, approximate computing has attracted attention as a method to reduce power and area for error-tolerant applicat... [more] | VLD2023-60 ICD2023-68 DC2023-67 RECONF2023-63 pp.156-161 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 15:00 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ) VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have ... [more] | VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 pp.25-30 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-27 11:00 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
A Block Partitioning Method to Accelerate Test Generation for Gate-Exhaustive Faults Momona Mizota, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) CPSY2022-3 DC2022-3 |
In gate-exhaustive fault model which covers defects in cells, since the number of faults is proportion to that of gates,... [more] | CPSY2022-3 DC2022-3 pp.13-18 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:50 |
Online | Online | A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) CPSY2021-57 DC2021-91 |
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] | CPSY2021-57 DC2021-91 pp.73-78 |
| DC | 2022-03-01 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] | DC2021-74 pp.57-62 |
| DC | 2021-12-10 13:00 |
Kagawa | (Primary: On-site, Secondary: Online) |
A Low Power Oriented Multiple Target Test Generation Method Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55 |
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] | DC2021-55 pp.1-6 |
| ICM | 2021-03-18 09:00 |
Online | Online | Proposal of Automatic Generation Method of API Adapter Test Code Sho Kanemaru, Yukitsugu Sasaki, Kensuke Takahashi, Tsuyoshi Toyoshima (NTT) ICM2020-59 |
In B2B2X (Business to Business to X) business model, the importance of API orchestrator for constructing and operating s... [more] | ICM2020-59 pp.1-6 |
| DC | 2021-02-05 14:00 |
Online | Online | Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74 |
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] | DC2020-74 pp.30-35 |
| CPSY, DC, IPSJ-ARC [detail] | 2020-07-31 15:45 |
Online | Online | A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12 |
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] | CPSY2020-12 DC2020-12 pp.75-80 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| DC | 2019-02-27 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Efficient Challenge-Response Pairs Generation and Evaluation for PUF Circuit Using BIST Circuit During Manufacturing Test Tomoki Mino, Shintani Michihiro, Michiko Inoue (NAIST) DC2018-75 |
Recently, counterfeited ICs have become a big problem for semiconductor supply chains. One of the countermeasures for th... [more] | DC2018-75 pp.25-30 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48 |
This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set ... [more] | VLD2018-74 CPSY2018-84 RECONF2018-48 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | On low power oriented test pattern compaction using SAT solver Yusuke Matsunaga (Kyushu Univ.) VLD2017-43 DC2017-49 |
This paper proposes a test pattern compaction method under power consumption constraint, which uses SAT solver based ... [more] |
VLD2017-43 DC2017-49 pp.95-99 |
| SIP, CAS, MSS, VLD | 2017-06-20 14:50 |
Niigata | Niigata University, Ikarashi Campus | SAT model sampling for test pattern generation considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 pp.107-112 |
| DC | 2017-02-21 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75 |
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI techn... [more] | DC2016-75 pp.7-10 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Fast Test Pattern Reordering Based on Weighted Fault Coverage Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.) VLD2016-61 DC2016-55 |
Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the ga... [more] | VLD2016-61 DC2016-55 pp.99-104 |
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