Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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ICD2013-1
[Invited Talk]
A Low Power Phase Change Memory Using Low Thermal Conductive Material with Nano-Crystalline Structure
Takahiro Morikawa, Ken'ichi Akita, Takasumi Ohyanagi, Masahito Kitamura, Masaharu Kinoshita, Mitsuharu Tai, Norikatsu Takaura (LEAP)
pp. 1 - 4
ICD2013-2
[Invited Talk]
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions
Koji Tsunoda, Hideyuki Noshiro, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Yoshihisa Iba, Akiyoshi Hatada, Masaaki Nakabayashi, Takashi Takenaga, Masaki Aoki, Toshihiro Sugii (LEAP)
pp. 5 - 10
ICD2013-3
[Invited Talk]
An Inductive-Coupling Wake-Up Transceiver for Standby Power Reduction of Non-Contact Memory Card
Noriyuki Miura (Kobe Univ.), Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda (Keio Univ.)
pp. 11 - 14
ICD2013-4
[Invited Talk]
Filament Scaling Forming Technique and Level-Verify-Write Scheme with Endurance Over 10 million Cycles in ReRAM
Akifumi Kawahara, Ken Kawai, Yuuichirou Ikeda, Yoshikazu Katoh, Ryotaro Azuma, Yuhei Yoshimoto, Kouhei Tanabe, Zhiqiang Wei, Takeki Ninomiya, Koji Katayama, Shunsaku Muraoka, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Kunitoshi Aono (Panasonic)
pp. 15 - 20
ICD2013-5
[Invited Talk]
Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies
Tetsuo Endoh (Tohoku Univ.)
pp. 21 - 26
ICD2013-6
[Invited Lecture]
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique
-- Achieves 1.0ns/200ps Wake-Up/Power-Off Times --
Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome (NEC), Shoji Ikeda, Takahiro Hanyu, Hideo Ohno (Tohoku Univ.)
pp. 27 - 32
ICD2013-7
[Invited Lecture]
Fabrication of a Nonvolatile TCAM Chip Based on 4T-2MTJ Cell Structure
Shoun Matsunaga (Tohoku Univ.), Sadahiko Miura, Hiroaki Honjo (NEC), Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.)
pp. 33 - 38
ICD2013-8
[Invited Talk]
Novel Vertical Magnetization STT-MRAM Technologies for Reducing Power of High Performance Mobile Processors
Shinobu Fujita, Keiko Abe, Hiroki Noguchi, Kumiko Nomura, Eiji Kitagawa, Naoharu Shimomura, Junichi Ito, Hiroaki Yoda (Toshiba)
pp. 39 - 40
ICD2013-9
Highly Reliable Logic Primitive Gates for Spintronics-Based Logic LSI
Yukihide Tsuji, Ryusuke Nebashi, Noboru Sakimura, Ayuka Morioka, Hiroaki Honjo, Keiichi Tokutome, Sadahiko Miura (NEC), Tetsuhiro Suzuki (Renesas Electronics Corp.), Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC)
pp. 41 - 46
ICD2013-10
Spin-Transfer Torque RAM Cache Energy Reduction Using Zero-Data Flags
Yuta Kimi, Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.)
pp. 47 - 52
ICD2013-11
[Panel Discussion]
Future prospects of memory solutions for smart society
-- Can new nonvolatile memories replace SRAM/DRAM/Flash? --
Koji Nii (Renesas Erctronics), Tetsuo Endoh (Tohoku Univ.), Yoshikazu Katoh (Panasonic), Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (Elpida Memory), Atsushi Kawasumi (Toshiba), Toru Miwa (SanDisk)
p. 53
ICD2013-12
[Invited Talk]
Complementary atom-switch based programmable cell array and its demostraion of logic mapping synthesized from RTL code
Makoto Miyamura, Munehiro Tada, Toshitsugu Sakamoto, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (LEAP)
pp. 55 - 59
ICD2013-13
[Invited Talk]
High Performance and High Reliability 40nm Embedded SG-MONOS Flash Macros for Automotive
-- 160MHz Random Access for Code and Endurance Over 10M Cycles for Data --
Tomoya Ogawa, Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi (Renesas Electronics)
pp. 61 - 66
ICD2013-14
[Invited Talk]
Unified Solid-State-Storage Architecture with NAND Flash Memory and ReRAM that Tolerates 32× Higher BER for Big-Data Applications
Shuhei Tanakamaru (Chuo Univ./Univ. of Tokyo), Masafumi Doi, Ken Takeuchi (Chuo Univ.)
pp. 67 - 72
ICD2013-15
[Invited Lecture]
A High Performance Storage Class Memory/MLC NAND Hybrid SSD with Anti-Fragmentation Algorithm
Kousuke Miyaji (Chuo Univ.), Hiroki Fujii (Univ. of Tokyo), Koh Johguchi (Chuo Univ.), Kazuhide Higuchi, Chao Sun (Univ. of Tokyo), Ken Takeuchi (Chuo Univ.)
pp. 73 - 78
ICD2013-16
[Invited Lecture]
Design of Vset/reset(3V), Vpgm(20V) generator system for 3D-ReRAM and NAND flash memory hybrid solid-state drives
Teruyoshi Hatanaka (Chuo Univ./Univ. of Tokyo), Koh Johguchi, Shogo Hachiya, Ken Takeuchi (Chuo Univ.)
pp. 79 - 84
ICD2013-17
[Invited Lecture]
An Integrated Variable Positive/Negative Temperature Coefficient Read Reference Generator for MLC PCM/NAND Hybrid 3D SSD
Kousuke Miyaji, Koh Johguchi (Chuo Univ.), Kazuhide Higuchi (Univ. of Tokyo), Ken Takeuchi (Chuo Univ.)
pp. 85 - 90
ICD2013-18
[Invited Talk]
A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba)
pp. 91 - 96
ICD2013-19
[Invited Lecture]
A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO
Miyako Shizuno, Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa (Toshiba)
pp. 97 - 102
ICD2013-20
[Invited Lecture]
A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges
Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo)
pp. 103 - 108
ICD2013-21
[Invited Lecture]
Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki (Renesas Electronics)
pp. 109 - 114
ICD2013-22
[Invited Lecture]
A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS
Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai (Renesas Electronics)
pp. 115 - 120
ICD2013-23
NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets
Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 121 - 126
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.