Online edition: ISSN 2432-6380
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VLD2022-73
Measured Evaluation of BTI Degradation in a 65nm FDSOI Process using Ring Oscillators with Same Circuit Structure
Daisuke Kikuta (KIT), Ryo Kishida (TPU), Kazutoshi Kobayashi (KIT)
pp. 1 - 6
VLD2022-74
Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test
Daisuke Goeda (KIT), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michihiro Shintani (KIT)
pp. 7 - 12
VLD2022-75
Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process
Yuta Shintani, Michiko Inoue (Naist), Michihiro Shintani (Kyoto Institute of Technology)
pp. 13 - 18
VLD2022-76
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices
Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT)
pp. 19 - 24
VLD2022-77
Circuit Optimization and Simulation Evaluation for Ultra-Low Voltage of LRPUF Using Manufacturing Variability of Leakage Current
Shunkichi Hata, Kimiyoshi Usami (SIT)
pp. 25 - 30
VLD2022-78
A Study on Interface Circuits for Burst Transfers from Synchronous to Asynchronous Circuits
Shogo Semba, Hiroshi Saito (UoA)
pp. 31 - 36
VLD2022-79
High fidelity mask pattern generation method by amplitude component evaluation
Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA)
pp. 37 - 42
VLD2022-80
A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation
Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA)
pp. 43 - 48
VLD2022-81
A Feature Vector Considering Characteristics of Optical System for Lithography Hotspot Detection
Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama (HCU)
pp. 49 - 54
VLD2022-82
Large-scale SAT Solution Search by FPGA Implementation of Attraction-Repulsion Control-Type Amoeba Algorithm
Hideharu Amano, Torao Okuyama (Keio Univ.), Kaori Okoda, Masashi Aono (Amoeba Energy)
pp. 55 - 60
VLD2022-83
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs
Tomohisa Kawakami, Chiharu Shiro (Ritsumeikan Univ.), Hiroki Nishikawa (Osaka Univ.), Kong Xiangbo, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 61 - 66
VLD2022-84
Routing with washing droplets in MEDA biochips
Shiro Chiharu (Ritsumei), Nishikawa hiroki (Osaka), Xiangbo Kong, Tomiyama Hiroyuki, Yamashita Shigeru (Ritsumei)
pp. 67 - 72
VLD2022-85
(See Japanese page.)
pp. 73 - 78
VLD2022-86
Implementation of power-outage tolerant VLSI system using asynchronous circuits
Masashi Imai (Hirosaki Univ.)
pp. 79 - 84
VLD2022-87
A Study and an Evaluation of the High Performance Deep Neural Network Inference circuit on FPGAs
Ryo Yamamoto, Kenya Sugihara, Yoshihiro Ogawa (Mitsubishi Electric)
pp. 85 - 90
VLD2022-88
(See Japanese page.)
pp. 91 - 96
VLD2022-89
Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution
Mineo Kaneko (JAIST)
pp. 97 - 102
VLD2022-90
Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis
Masayuki Usui, Shinya Takamaeda (UTokyo)
pp. 103 - 108
VLD2022-91
[Memorial Lecture]
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects
Takuma Nagao (NAIST), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing), Michiko Inoue (NAIST), Michihiro Shintani (Kyoto Institute of Technology)
p. 109
VLD2022-92
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology
Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC)
p. 110
VLD2022-93
[Memorial Lecture]
DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture]
Dehua Liang (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.), Noriyuki Miura, Jun Shiomi (Osaka Univ.)
p. 111
VLD2022-94
[Memorial Lecture]
A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers
Kyehei Seino, Shigeru Yamashita (Ritsumeikan University)
p. 112
VLD2022-95
Secure Cache System against On-Chip Threats
Keisuke Kamahori, Shinya Takamaeda (UTokyo)
pp. 113 - 118
VLD2022-96
Hiding Memory Structure for IP Protection
Sun Tanaka, Shinya Takamaeda (UTokyo)
pp. 119 - 124
VLD2022-97
Multiple Constant Convolution with Minimum Number of Full Adders.
Kota Kuga, Shinya Takamaeda (UTokyo)
pp. 125 - 130
VLD2022-98
Reducing Conflict Misses with Multiple Indexings in Compressed Caches
Tasuku Fukami, Shinya Takamaeda (UTokyo)
pp. 131 - 136
VLD2022-99
Communication-Efficient Federated Learning with Gradient Boosting Decision Trees
Kotaro Shimamura, Shinya Takamaeda (UTokyo)
pp. 137 - 142
VLD2022-100
Global routing method imitating car path search
Yusuke Yamaguchi, Kunihiro Fujiyoshi (TUAT)
pp. 143 - 148
VLD2022-101
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat)
pp. 149 - 154
VLD2022-102
Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT)
pp. 155 - 160
VLD2022-103
Yusei Yano, Shinji Nozaki, Tomohide Aizawa, Yukihide Kohira (Univ. of Aizu)
pp. 161 - 166
VLD2022-104
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.)
pp. 167 - 172
VLD2022-105
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
pp. 173 - 178
VLD2022-106
High-Performance and Programmer-Friendly Secure Non-Volatile Memory using Temporal Memory-Access Redirection
Ryo Koike, Shinya Takamaeda (UTokyo)
pp. 179 - 184
VLD2022-107
A Logic Locking Method based on Function Modification Circuit
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.)
pp. 185 - 190
VLD2022-108
N/A
Yuka Ikegami, Kazuki Yamashita (Waseda Univ.), Kento Hasegawa, Kazuhide Fukushima, Shinsaku Kiyomoto (KDDI Research, Inc.), Nozomu Togawa (Waseda Univ.)
pp. 191 - 196
VLD2022-109
Toggle-based simulation of side-channel attack against multiplier for pairing-based cryptography
Saito Kikuoka, Makoto Ikeda (Tokyo Univ.)
pp. 197 - 202
VLD2022-110
Design optimization of TFHE-based 4+ input homomorphic logic gates by error controlling
Yinfan Zhao, Makoto Ikeda (Tokyo Univ.)
pp. 203 - 208
VLD2022-111
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA
Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
pp. 209 - 214
VLD2022-112
NA
Ryusei Eda, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
pp. 215 - 220
VLD2022-113
NA
Hibiki Nakanishi, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
pp. 221 - 226
VLD2022-114
NA
Takuma Yabe, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
pp. 227 - 232
VLD2022-115
Importance of Inverters Placement in Ring-Oscilator for Laser Irradiation Detection
Shungo Hayashi (YNU), Junichi Sakamoto (AIST/YNU), Masaki Chikano, Tsutomu Matsumoto (YNU)
pp. 233 - 238
VLD2022-116
Fundamental study of distance spoofing attack against dToF lidar with interference mitigation function
Midori Tomijima, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
pp. 239 - 244
VLD2022-117
Clone Resistance of Artifact Metrics: Scanning Probe Lithography Based Clones
Naoki Yoshida, Akira Iwahashi (YNU), Hoga Morihisa, Junko Ohta, Kaoru Sumiya (AIST), Tsutomu Matsumoto (YNU)
pp. 245 - 250
VLD2022-118
Clone Resistance of Artifact Metrics Systems Based on White Light Interferometry and Phase Only Correlation
Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU)
pp. 251 - 256
VLD2022-119
Cloud Based Evaluation of Communication Bandwidth and Tracking Time of Traceable Aggregate Signature Protocols
Koudai Aoyama, Riku Anzai, Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (Yokohama National Univ.)
pp. 257 - 260
VLD2022-120
Threat of EM Information Leakage from Speakerphones Due to IEMI and Suppression Indexes for EMC Countermeasures
Seiya Takano, Yuichi Hayashi (NAIST)
pp. 261 - 266
VLD2022-121
*
Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Nagata Makoto (Kobe Univ.)
pp. 267 - 272
VLD2022-122
Side-channel Information Leakage Resistance Evaluation of Cryptographic Multi- chip Modules
Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.)
pp. 273 - 278
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.