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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MSS, CAS, SIP, VLD | 2020-06-18 14:00 |
Online | Online | Optimal Design for Level-Shifter-Less Approach using Channel Length Modulation & Body Biasing Tatsuya Watanabe, Usami Kimiyoshi (SIT)  CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 |
A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this de... [more] | CAS2020-8 VLD2020-8 SIP2020-24 MSS2020-8 pp.41-46 |
| HWS, VLD | 2019-02-28 10:50 |
Okinawa | Okinawa Ken Seinen Kaikan | Single Supply Level Shifter Circuit using body-bias Yuki Takeyoshi, Kimiyoshi Usame (SIT) VLD2018-109 HWS2018-72 |
A multi-VDD scheme exists as a technique to realize low power consumption by using different power supply voltages. A ci... [more] | VLD2018-109 HWS2018-72 pp.97-102 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 13:10 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB) Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech) VLD2016-47 DC2016-41 |
Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with di... [more] | VLD2016-47 DC2016-41 pp.19-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-53 DC2016-47 |
We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper des... [more] | VLD2016-53 DC2016-47 pp.55-60 |
| SDM | 2016-10-26 15:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2016-71 pp.15-20 |
| SDM | 2016-10-26 16:10 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias Yoshiki Yamamoto, Hideki Makiyama, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Shinkawata Hiroki, Shiro Kamohara, Yasuo Yamaguchi (Renesas), Nobuyuki Sugii (Hitachi), Tomoko Mizutani, Toshiro Hiramoro (UT) SDM2016-72 |
We demonstrated record 0.37V minimum operation voltage (VMIN) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks... [more] | SDM2016-72 pp.21-25 |
| VLD | 2016-03-01 16:40 |
Okinawa | Okinawa Seinen Kaikan | Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX. Hanano Suzuki, Kimiyoshi Usami (Shibaura IT) VLD2015-129 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-129 pp.105-110 |
| VLD | 2016-03-01 17:05 |
Okinawa | Okinawa Seinen Kaikan | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) VLD2015-130 |
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] | VLD2015-130 pp.111-116 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT) VLD2015-88 CPSY2015-120 RECONF2015-70 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-88 CPSY2015-120 RECONF2015-70 pp.91-96 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 10:30 |
Kanagawa | Hiyoshi Campus, Keio University | Power Optimization of a Reconfigurable Accelerator by Middle-grained Body Bias Control Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.) VLD2015-101 CPSY2015-133 RECONF2015-83 |
(To be available after the conference date) [more] | VLD2015-101 CPSY2015-133 RECONF2015-83 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP) CPM2015-134 ICD2015-59 |
The leakage has been increasing by miniaturization of the transistor in recently year. Adaptive body bias generator with... [more] | CPM2015-134 ICD2015-59 pp.39-43 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:00 |
Kanagawa | Hiyoshi Campus, Keio University | Temperature sensor applying Body Bias in Silicon-on-Thin-BOX Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) VLD2014-127 CPSY2014-136 RECONF2014-60 |
The performance advancement by the transistor scaling is blocked by increase of power consumption and process variation.... [more] | VLD2014-127 CPSY2014-136 RECONF2014-60 pp.99-104 |
| SDM | 2014-10-17 14:30 |
Miyagi | Niche, Tohoku Univ. | [Invited Talk]
Back-Bias Control technique for Suppression of Die-to-Die Delay Variability of SOTB MOS Circuits at Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Yasuo Yamaguchi (LEAP), Koichiro Ishibashi (Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo) SDM2014-94 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2014-94 pp.61-68 |
| VLD | 2014-03-05 13:50 |
Okinawa | Okinawa Seinen Kaikan | Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-162 |
Silicon on thin BOX(SOTB) is one of FD-SOI device.It is possible to operate with ultra-low voltage of 0.4V and greatly c... [more] | VLD2013-162 pp.153-158 |
| SDM | 2014-01-29 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii (LEAP), Koichiro Ishibashi (Univ. of Electro- Comm.), Tomoko Mizutani, Toshiro Hiramoto (Univ. of Tokyo), Yasuo Yamaguchi (LEAP) SDM2013-143 |
Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation volta... [more] | SDM2013-143 pp.35-38 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 17:00 |
Kanagawa | Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] | VLD2012-120 CPSY2012-69 RECONF2012-74 pp.75-80 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) VLD2012-70 DC2012-36 |
Designing reliable systems has become more difficult in recent years. In this paper, statistical nature of RTN-induced ... [more] |
VLD2012-70 DC2012-36 pp.63-68 |
| ICD, SDM | 2012-08-02 13:00 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Lecture]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, The University of Tokyo) SDM2012-68 ICD2012-36 |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation (ULV) CMOS with maximum power efficien... [more] | SDM2012-68 ICD2012-36 pp.29-32 |
| SDM, ED (Workshop) |
2012-06-29 09:45 |
Okinawa | Okinawa Seinen-kaikan | [Invited Talk]
Silicon on Thin Buried Oxide (SOTB) Technology for Ultralow-Power (ULP) Applications Nobuyuki Sugii, Toshiaki Iwamatsu, Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Hirofumi Shinohara, Hideki Aono, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi (LEAP/Renesas), Tomoko Mizutani, Toshiro Hiramoto (IIS, Univ. of Tokyo) |
Needs for low-power CMOS devices are still increasing. Ultralow-voltage-operation CMOS with maximum power efficiency can... [more] | |
| VLD | 2012-03-07 16:05 |
Oita | B-con Plaza | Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-144 |
Power Gating (PG) is one of the technologies for reducing leakage energy. The effectiveness of leakage energy reduction ... [more] | VLD2011-144 pp.145-150 |
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