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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-01 14:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Defect Coverage Estimation by Sampling in Testing Power TSV Koutaro Hachiya, Yudai Kawakami (THU)  VLD2023-129 HWS2023-89 ICD2023-118 |
As a test for power TSVs (Through Silicon Via) in 3D-IC, a method has been proposed to detect open defects by placing po... [more] | VLD2023-129 HWS2023-89 ICD2023-118 pp.157-160 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| CPM | 2021-10-27 10:30 |
Online | Online | Study on the low-temperature deposition method of SiNx film for Cu-TSV Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.) CPM2021-21 |
For Cu through silicon via in the 3D-LSI, It is desired to realize a deposition method of an insulating film less than 2... [more] | CPM2021-21 pp.5-7 |
| SDM | 2019-02-07 11:25 |
Tokyo | [Invited Talk]
Ultrafine 3D Interconnect Technology Using Directed Self-Assembly Takafumi Fukushima, Murugesan Mariappan, Mitsumasa Koyanagi (Tohoku Univ.) SDM2018-92 |
A directed self-assembly (DSA) technology is applied to fabricate ultrafine pitch TSV (Through-Silicon Vias) for ultra-h... [more] | SDM2018-92 pp.5-8 |
|
| SDM | 2019-02-07 13:10 |
Tokyo | [Invited Talk]
Stress Investigation of Annular-Trench-Isolated (ATI) Through Silicon Via (TSV) Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi (AIST) SDM2018-93 |
The methods as parylene substitute of SiO2 as dielectric layer and annular structure lose efficacy for thermal stress re... [more] | SDM2018-93 pp.9-14 |
|
| EMCJ, IEE-EMC, IEE-MAG | 2018-11-22 14:20 |
Overseas | KAIST | A Novel Eye-Diagram Estimation Method for Pulse Amplitude Modulation with N-level on Stacked Through Silicon Vias Junyong Park, Youngwoo Kim, Kyungjun Cho, Seongsoo Lee, Joungho Kim (KAIST) EMCJ2018-64 |
This paper proposed an eye-diagram estimation method for pulse amplitude modulation with N-level signaling. For verifica... [more] | EMCJ2018-64 p.29 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 |
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] | CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 pp.167-172 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Thermal Analysis in 3D ICs Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 |
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] | CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 pp.173-178 |
| EMCJ, IEE-EMC, IEE-MAG | 2016-06-02 16:10 |
Overseas | NTU, Taiwan | [Invited Talk]
Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range Kuan-Chung Lu, Tzyy-Sheng Horng (National Sun Yat-sen Univ.) EMCJ2016-35 |
The advantages of vertical interconnects include superior electrical transmissions for stacked dies, higher I/O density,... [more] | EMCJ2016-35 pp.57-62 |
| CPM | 2015-11-06 15:15 |
Niigata | Machinaka Campus Nagaoka | Properties of transition metal nitride deposited by combination of sputtering and radical treatment Mayumi B. Takeyama, Masaru Sato (Kitami Inst. of Technol.), Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (Kitami Inst. of Technol.) CPM2015-89 |
We have proposed the low temperature deposition method of preparing transition metal nitride films by combination of spu... [more] | CPM2015-89 pp.27-30 |
| CPM | 2015-08-11 09:40 |
Aomori | Low temperature deposition of HfNx film by radical reaction Masaru Sato, Mayumi B. Takeyama, Atsushi Noya (Kitami inst. of Technol.) CPM2015-40 |
We have demonstrated the preparation of a low-temperature deposited HfNx film as a diffusion barrier applicable to the C... [more] | CPM2015-40 pp.47-50 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26 |
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] | VLD2014-72 DC2014-26 pp.3-8 |
| SDM | 2014-02-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
TSV Liner Formation with Vapor Deposited Polyimides Takafumi Fukushima, Mariappan Murugesan, Jicheol Bea, Kangwook Lee, Mitsumasa Koyanagi (Tohoku Univ.) SDM2013-172 |
A Kapton insulation layer as a TSV liner was conformably formed by vapor deposition polymerization with pyromellitic dia... [more] | SDM2013-172 pp.39-42 |
| CAS, NLP | 2013-09-26 12:40 |
Gifu | Satellite Campus, Gifu University | Efficient Transient Analysis of 3-D Stacked On-Chip Power Distribution Network with Power/Ground Through Silicon Vias by Using Block Latency Insertion Method Daisei Nagata, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2013-36 NLP2013-48 |
In this report, we apply the block latency insertion method (block-LIM) to the transient analysis of on-chip power distr... [more] | CAS2013-36 NLP2013-48 pp.1-6 |
| SDM, ICD | 2013-08-01 13:45 |
Ishikawa | Kanazawa University | [Invited Talk]
Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET) SDM2013-71 ICD2013-53 |
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] | SDM2013-71 ICD2013-53 pp.31-34 |
| ICD | 2011-04-19 14:00 |
Hyogo | Kobe University Takigawa Memorial Hall | 1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL) ICD2011-15 |
A novel multicore DRAM architecture with an ultra high bandwidth and a large capacity is proposed for high throughput co... [more] | ICD2011-15 pp.81-86 |
| ICD, SDM | 2010-08-26 13:00 |
Hokkaido | Sapporo Center for Gender Equality | 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) SDM2010-131 ICD2010-46 |
A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architect... [more] | SDM2010-131 ICD2010-46 pp.39-44 |
| CPM | 2010-07-30 09:30 |
Hokkaido | Michino-Eki Shari Meeting Room | Low temperature of deposition of ZrNx film using radical reaction Masaru Sato, Mayumi B. Takeyama (kitami Inst. of Tech.), Yuichiro Hayasaka, Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (kitami Inst. of Tech.) CPM2010-36 |
Recently, an increase in the integration density of the Si-ULSI system is realized in the 3-D packaging technology. A t... [more] |
CPM2010-36 pp.29-34 |
| SDM | 2009-10-29 15:30 |
Miyagi | Tohoku University | Silicon Wafer Thinning Technology for Three-Dimensional Integrated Circuit by Wet Etching Kazuhiro Yoshikawa, Tomotsugu Ohashi, Tatsuro Yoshida, Takenao Nemoto, Tadahiro Ohmi (Tohoku Univ.) SDM2009-120 |
A three-dimensional integrated circuit is developed as an emerging technology in a semiconductor industry. The silicon w... [more] | SDM2009-120 pp.15-19 |
| CPM | 2009-08-11 11:15 |
Aomori | Hirosaki Univ. | Effectiveness of New Deposition Method for Barrier Metal Applicable to Through Silicon Via
-- Properties of ZrNx Film Formed at Low Temperature -- Masaru Sato, Mayumi B. Takeyama (Kitami Inst. of Tech.), Yuichiro Hayasaka, Eiji Aoyagi (Tohoku Univ.), Atsushi Noya (Kitami Inst. of Tech.) CPM2009-44 |
A low process temperature as low as 200°C is one of the most important requirements for the metallization technology of ... [more] | CPM2009-44 pp.57-60 |
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