Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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DC2009-30
Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis
Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST)
pp. 13 - 18
DC2009-31
A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System
Kazuhito Ito, HyunJoon Kim (Saitama Univ.)
pp. 19 - 24
DC2009-32
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI
Hidekazu Seto, Kazuhito Ito (Saitama Univ.)
pp. 25 - 30
DC2009-33
Evaluation of Hardware/Software Partitioning Method with Consideration of Timing
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.)
pp. 31 - 36
DC2009-34
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 37 - 42
DC2009-35
Simulation-Based Bus Width Optimization for Two-Level Cache
Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 43 - 48
DC2009-36
An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
pp. 55 - 60
DC2009-37
BILBO register with Soft Error Detection Function
Masahiro Sugasawa, Kazuteru Namba, Hideo Ito (Chiba Univ.)
pp. 61 - 66
DC2009-38
An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism
Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo)
pp. 67 - 72
DC2009-39
A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures
Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ)
pp. 73 - 78
DC2009-40
Detection of Fault Candidate portions by DEF data Visualization
Kazuaki Kishi, Masaru Sanada (Kochi Univ. of Tech.)
pp. 85 - 88
DC2009-41
A Yield Model with Testability and Repairability
Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 89 - 94
DC2009-42
Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity
Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST)
pp. 95 - 100
DC2009-43
Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 101 - 105
DC2009-44
A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter
Kimio Shibata, Cong-Kha Pham (Univ. of Electro-Comm.)
pp. 107 - 111
DC2009-45
A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)
pp. 119 - 124
DC2009-46
Increasing Yield Using Partially-Programmable Circuits
Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
pp. 125 - 130
DC2009-47
Transistor-Array-Based Opamp Layout and its Evaluationon
Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 131 - 136
DC2009-48
Analysis of Layout Structure Dependence on Distance/Space Variation for MOS Transistors
Yuichi Sadohira, Shigetoshi Nakatake (Univ. of Kitakyusyu)
pp. 137 - 142
DC2009-49
A Test Compaction Oriented Don't Care Identification Method
Motohiro Wakazono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 149 - 154
DC2009-50
A secure design for testability of RSA Encryption circuits
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 155 - 160
DC2009-51
Logic stabilization way of open fault with unsuitable logic
-- Aim in simple diagnosis technology --
Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.)
pp. 161 - 166
DC2009-52
A Path Selection Method of Delay Test for Transistor Aging
Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST)
pp. 167 - 172
DC2009-53
Evaluation of Energy Consumption on Multipliers Using the Sum of Operands
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.)
pp. 173 - 178
DC2009-54
Automatic Generation of Design-Specific Cell Libraries
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
pp. 179 - 184
DC2009-55
FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 185 - 190
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.