Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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CPSY2013-73
Design and implementation of high-level synthesis compiler for stream computation
Ryo Ito, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 1 - 6
CPSY2013-74
A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs
Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.)
pp. 7 - 12
CPSY2013-75
Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench
Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Takuji Mitsuishi, Hideharu Amano (Keio Univ.)
pp. 13 - 18
CPSY2013-76
a discussion on hardware architecture of SIFT algorithm for FPGAs utilizing a high-level synthesis tool
Naohisa Arakawa, Lin Meng, Tomonori Izumi (Ritsumeikan Univ.)
pp. 19 - 24
CPSY2013-77
A Storing and Regenerating Signal Information in a Scalable Hardware System
Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech)
pp. 25 - 30
CPSY2013-78
Hardware Expansion Protocol in a Scalable Hardware System
Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.)
pp. 31 - 36
CPSY2013-79
A FPGA/GPU cooperation in nodes communication using PEACH2
Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Tokyo Univ.), Hideharu Amano (Keio Univ.), Taisuke Boku (Univ. of Tsukuba)
pp. 37 - 42
CPSY2013-80
Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption
Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.)
pp. 43 - 48
CPSY2013-81
[Invited Talk]
Research on VLSI Circuits
-- From Solving Problem to Creating Future --
Tadahiro Kuroda (Keio Univ.)
pp. 49 - 54
CPSY2013-82
The Improvement of Auto-Sharding in MongoDB with Priority-Chunk
Yasuhiro Sato, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.)
pp. 55 - 60
CPSY2013-83
Improving the Preformance of Virtual Machine Live Migration by Ordering Memory Page Transfer on Access Pattern
Shintaro Nakai, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.)
pp. 61 - 66
CPSY2013-84
A Vertical Link On/Off Algorithm for Wireless 3-D NoCs
Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
pp. 67 - 72
CPSY2013-85
A Case for Low-Power Networks using FSO and On/Off Links
Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
pp. 73 - 78
CPSY2013-86
A 3D FPGA-Array "Vocalise" and its communication system.
Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Akihiro Sorimachi, Baku Ogasawara, Masatoshi Sekine (TUAT)
pp. 79 - 84
CPSY2013-87
An Image Recognition System with Multi-Resolutional Feature Learning on the 3D FPGA-Array "Vocalise"
Baku Ogasawara, Satoru Yokota, Jiang Li, Yusuke Atsumari, Hiromasa Kubo, Masatoshi Sekine (TUAT)
pp. 85 - 90
CPSY2013-88
Double Caching Memcached Accelerator
Eric Shun Fukuda, Tsunaki Sadahisa (Hokkaido Univ.), Hiroaki Inoue, Takashi Takenaka (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
pp. 91 - 96
CPSY2013-89
A study on module allocation in multi-FPGA systems
Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus)
pp. 97 - 102
CPSY2013-90
An Experimental Bit-Parallel Solution to Accelerate Smith-Waterman Algorithm
Saori Sudo, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC)
pp. 103 - 108
CPSY2013-91
Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA
Satoshi Haramura, Hiroto Kagotani, Yasuyuki Nogami, Yuji Sugiyama (Okayama Univ.)
pp. 109 - 112
CPSY2013-92
Performance Evaluation of Graph Database using Multicore and GPU
Shin Morishima, Hiroki Matsutani (Keio Univ.)
pp. 113 - 118
CPSY2013-93
Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.)
pp. 119 - 124
CPSY2013-94
A configurable switch mechanism for random NoCs
Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 125 - 130
CPSY2013-95
Implementation and Evaluation of Multi-stream Bandwidth Compressor
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 131 - 136
CPSY2013-96
Study of accelerator connection using the peripheral bus of OpenMSP430
Ayano Fukuju, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 137 - 142
CPSY2013-97
A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems
Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT)
pp. 143 - 148
CPSY2013-98
On Boolean Matching of LUT-based Circuits
Yusuke Matsunaga (Kyushu Univ.)
pp. 149 - 154
CPSY2013-99
Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency
Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 155 - 160
CPSY2013-100
Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA
Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
pp. 161 - 166
CPSY2013-101
A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design
Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
pp. 167 - 172
CPSY2013-102
Methodology for NBTI measurement using an on-chip leakage monitor circuit
Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 173 - 178
CPSY2013-103
PerCUDA: CUDA Binding Framework for Perl
Takayuki Fukumoto, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 179 - 184
CPSY2013-104
Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU
Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 185 - 190
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.