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| Chair |
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Noriyuki Minegishi (Mitsubishi Electric) |
| Vice Chair |
|
Nozomu Togawa (Waseda Univ.) |
| Secretary |
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Koyo Nitta (NTT), Yukihide Odaira (Aizu Univ.) |
|
|
|
| Chair |
|
Fumihiko Hirose (Yamagata Univ.) |
| Vice Chair |
|
Mayumi Takeyama (Kitami Inst. of Tech.) |
| Secretary |
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Yuichi Nakamura (Toyohashi Univ. of Tech.), Yuichi Akage (NTT) |
| Assistant |
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Yasuo Kimura (Tokyo Univ. of Tech.), Hideki Nakazawa (Hirosaki Univ.), Tomoaki Terasako (Ehime Univ.) |
|
|
|
| Chair |
|
Hideto Hidaka (Renesas) |
| Vice Chair |
|
Makoto Nagata (Kobe Univ.) |
| Secretary |
|
Takashi Hashimoto (Panasonic), Masanori Natsui (Tohoku Univ.) |
| Assistant |
|
Hiroyuki Ito (Tokyo Inst. of Tech.), Masatoshi Tsuge (Socionext), Tetsuya Hirose (Kobe Univ.) |
|
|
|
| Chair |
|
Takayuki Hamamoto (Tokyo Univ. of Science) |
| Vice Chair |
|
Hideaki Kimata (NTT), Kazuya Kodama (NII) |
| Secretary |
|
Kei Kawamura (KDDI Research), Keita Takahashi (Nagoya Univ.) |
| Assistant |
|
Kazuya Hayase (NTT), Yasutaka Matsuo (NHK) |
|
|
|
| Chair |
|
Koji Nakano (Hiroshima Univ.) |
| Vice Chair |
|
Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu) |
| Secretary |
|
Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.) |
| Assistant |
|
Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.) |
|
|
|
| Chair |
|
Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| Vice Chair |
|
Hiroshi Takahashi (Ehime Univ.) |
| Secretary |
|
Haruhiko Kaneko (Tokyo Inst. of Tech.), Masayuki Arai (Nihon Univ.) |
|
|
|
| Chair |
|
Masato Motomura (Hokkaido Univ.) |
| Vice Chair |
|
Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (RIKEN) |
| Secretary |
|
Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) |
| Assistant |
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Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) |
|
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|
| Secretary |
|
Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Univ. of Tokyo), Yohei Hasegawa (Toshiba Memory) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Yutaka Tamiya (Fujitsu Laboratories) |
| Secretary |
|
Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.) |
| Assistant |
|
Hiroe Iwasaki (NTT) |
|
| Conference Date |
Wed, Dec 5, 2018 09:30 - 17:30
Thu, Dec 6, 2018 09:00 - 20:30
Fri, Dec 7, 2018 09:00 - 16:55 |
| Topics |
Design Gaia 2018 -New Field of VLSI Design- |
| Conference Place |
Satellite Campus Hiroshima |
| Address |
1-5-3 Otemachi, Naka-ku Hiroshima-shi, Hiroshima-ken 730-0051 Japan |
| Transportation Guide |
http://www.pu-hiroshima.ac.jp/site/satellite/ |
Contact
Person |
Prof. Shinobu Nagayama, Hiroshima City University, Japan
+81-82-830-1599 |
| Sponsors |
This conference is supported by IEEE CEDA All Japan Joint Chapter and IEEE CAS Japan Joint Chapter.
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, DC, CPSY, RECONF, CPM, ICD, IE. |
Wed, Dec 5 AM
09:30 - 10:45 |
(1)
VLD |
09:30-09:55 |
Design Automation and Optimal Architecture of NLoC  VLD2018-40 DC2018-26 |
Yuto Umeda, Shigeru Yamashita (Ritsumeikan Univ.) |
(2)
VLD |
09:55-10:20 |
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones VLD2018-41 DC2018-27 |
Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(3)
VLD |
10:20-10:45 |
Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning VLD2018-42 DC2018-28 |
Takumi Okamoto, Masayuki Odagawa, Koujiroh Takebayashi, Mikihisa Nagano, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ.), Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba (Cadence, Japan) |
Wed, Dec 5 AM
09:55 - 10:45 |
(4)
RECONF |
09:55-10:20 |
Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA RECONF2018-34 |
Kotaro Tamura, Tetsu Narumi (UEC univ.) |
(5)
RECONF |
10:20-10:45 |
An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL RECONF2018-35 |
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) |
Wed, Dec 5 AM
09:55 - 10:45 |
| (6) |
09:55-10:20 |
|
| (7) |
10:20-10:45 |
|
| |
10:45-11:00 |
Break ( 15 min. ) |
Wed, Dec 5 AM
11:00 - 12:00 |
| (8) |
11:00-12:00 |
[Keynote Address]
Challenge of Post CMOS Circuit Technologies for AI Hardware |
Takahiro Hanyu (Tohoku Univ.) |
| |
12:00-13:00 |
Lunch Break ( 60 min. ) |
Wed, Dec 5 PM
13:00 - 14:00 |
| (9) |
13:00-14:00 |
[Keynote Address]
VLD2018-43 CPM2018-87 ICD2018-48 IE2018-66 CPSY2018-36 DC2018-29 RECONF2018-36 |
Hiroki Nakahara (Titech) |
| |
14:00-14:15 |
Break ( 15 min. ) |
Wed, Dec 5 PM
14:15 - 15:30 |
(10)
VLD |
14:15-14:40 |
Basic Evaluation of Netlist Function Inference using GCN VLD2018-44 DC2018-30 |
Hiroki Oyama, Motoki Amagasaki, Masahiro Iida (kumamoto Univ.), Hiroaki Yasuda, Hiroto Ito (MITSUBISHI ELECTRIC ENGINEERING) |
(11)
VLD |
14:40-15:05 |
Improved Routing Method for Two Layer Self-Aligned Double Patterning VLD2018-45 DC2018-31 |
Shoya Tamura, Kunihiro Fujiyoshi (TUAT) |
(12)
VLD |
15:05-15:30 |
Horizontal Wireless Bus for Free-Form SiP VLD2018-46 DC2018-32 |
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai (The Univ. of Tokyo) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Wed, Dec 5 PM
15:45 - 17:30 |
| |
- |
|
Thu, Dec 6 AM
09:00 - 10:15 |
(13)
RECONF |
09:00-09:25 |
Resources Utilization of Fine-grained Overlay Architecture RECONF2018-37 |
Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) |
(14)
RECONF |
09:25-09:50 |
Transparent Acceleration Method for Network Function Virtualization Using FPGA RECONF2018-38 |
Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC) |
(15)
RECONF |
09:50-10:15 |
An Evaluation of Acceleration Framework to Exploit TCAM implemented on FPGA RECONF2018-39 |
Takefumi Miyoshi (WasaLab/e-trees.Japan), Satoshi Funada (e-trees.Japan) |
Thu, Dec 6 AM
09:00 - 10:15 |
| (16) |
09:00-09:25 |
|
| (17) |
09:25-09:50 |
|
| (18) |
09:50-10:15 |
|
Thu, Dec 6 AM
09:00 - 10:15 |
(19)
VLD |
09:00-09:25 |
Stochastic Number Generation Considering Trade-off between Error and Overhead VLD2018-47 DC2018-33 |
Yudai Sakamoto, Shigeru Yamashita (Ritsumeikan Univ.) |
(20)
VLD |
09:25-09:50 |
Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD VLD2018-48 DC2018-34 |
Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.) |
(21)
VLD |
09:50-10:15 |
Secure PUF Authentication Method against Machine Learning Attack VLD2018-49 DC2018-35 |
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Thu, Dec 6 AM
10:30 - 11:45 |
(22)
RECONF |
10:30-10:55 |
Multi-FPGA implementation of deep learning applications RECONF2018-40 |
Kazusa Musha, Akram Ben Ahmed (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) |
(23)
RECONF |
10:55-11:20 |
A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique RECONF2018-41 |
Akira Jinguji, Simpei Sato, Hiroki Nakahara (titech) |
(24)
RECONF |
11:20-11:45 |
Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder RECONF2018-42 |
Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech) |
Thu, Dec 6 AM
10:30 - 11:45 |
(25)
DC |
10:30-10:55 |
VLD2018-50 DC2018-36 |
|
(26)
DC |
10:55-11:20 |
On the Generation of Random Capture Safe Test Vectors Using Neural Networks VLD2018-51 DC2018-37 |
Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) |
(27)
DC |
11:20-11:45 |
VLD2018-52 DC2018-38 |
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Thu, Dec 6 AM
10:30 - 11:45 |
(28)
VLD |
10:30-10:55 |
A Case Study on Memory Architecture Exploration for FPGA-based Manycores VLD2018-53 DC2018-39 |
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(29)
VLD |
10:55-11:20 |
Improved Thread Execution for GPU-oriented OpenCL Programs on Multicore Processors VLD2018-54 DC2018-40 |
Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo (Ritsumeikan Univ), Naohisa Hojo (Osaka Univ), Hiroyuki Tomiyama (Ritsumeikan Univ) |
(30)
VLD |
11:20-11:45 |
An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server VLD2018-55 DC2018-41 |
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Dec 6 PM
13:00 - 13:45 |
(31)
CPSY |
13:00-13:45 |
[Invited Talk]
What I should do beside dedicated AI hardwares CPSY2018-37 |
Yasuhiko Nakashima (NAIST) |
Thu, Dec 6 PM
13:00 - 14:40 |
(32)
DC |
13:00-13:25 |
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC VLD2018-56 DC2018-42 |
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(33)
DC |
13:25-13:50 |
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips VLD2018-57 DC2018-43 |
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) |
(34)
DC |
13:50-14:15 |
Study on the Applicability of ATPG Pattern for DFT Circuit VLD2018-58 DC2018-44 |
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(35)
DC |
14:15-14:40 |
Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis VLD2018-59 DC2018-45 |
Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Thu, Dec 6 PM
13:00 - 14:15 |
(36)
VLD |
13:00-13:25 |
An efficient SAT-attack algorithm against logic encryption VLD2018-60 DC2018-46 |
Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
(37)
VLD |
13:25-13:50 |
A Hybrid Method Using Monte-Carlo Tree Search and Gibbs Sampling Method for Solving Motif Extraction Problems VLD2018-61 DC2018-47 |
Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (HCU) |
(38)
VLD |
13:50-14:15 |
VLD2018-62 DC2018-48 |
Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
Thu, Dec 6 PM
14:00 - 14:50 |
(39)
RECONF |
14:00-14:25 |
Triple modular redundancy optically reconfigurable gate array RECONF2018-43 |
Toru Yoshinaga, Minoru Watanabe (Shizuoka Univ.) |
(40)
RECONF |
14:25-14:50 |
FPGA implementation of a robot control algorithm RECONF2018-44 |
Yusuke Takaki, Minoru Watanabe (Shizuoka Univ.), Kentaro Sano (Riken) |
Thu, Dec 6 PM
14:30 - 15:15 |
| (41) |
14:30-15:15 |
|
Thu, Dec 6 PM
14:55 - 16:10 |
(42)
ICD |
14:55-15:20 |
Design guideline of ground structure in slow wave transmission line CPM2018-88 ICD2018-49 IE2018-67 |
Tomohiro Kobayashi, Syuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ) |
(43)
ICD |
15:20-15:45 |
Millimeter wave band CMOS low noise amplifier design CPM2018-89 ICD2018-50 IE2018-68 |
Kyoya Takegawa, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
(44)
ICD |
15:45-16:10 |
Design method of millimeter wave CMOS amplifier circuit with flat frequency characteristics CPM2018-90 ICD2018-51 IE2018-69 |
Shota Kohara, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
Thu, Dec 6 PM
15:30 - 16:15 |
| (45) |
15:30-16:15 |
|
Thu, Dec 6 PM
15:30 - 16:45 |
| (46) |
15:30-15:55 |
|
(47)
VLD |
15:55-16:20 |
Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores VLD2018-63 DC2018-49 |
Hiroki Nishikawa, Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(48)
VLD |
16:20-16:45 |
Communication-Aware Scheduling for Data-Parallel Tasks VLD2018-64 DC2018-50 |
Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
Thu, Dec 6 PM
18:30 - 20:30 |
| |
- |
|
Fri, Dec 7 AM
09:00 - 10:15 |
(49)
CPSY |
09:00-09:25 |
A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks CPSY2018-38 |
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
| (50) |
09:25-09:50 |
|
| (51) |
09:50-10:15 |
|
Fri, Dec 7 AM
09:25 - 10:15 |
(52)
ICD |
09:25-09:50 |
Design method of millimeter wave CMOS oscillator with high efficiency CPM2018-91 ICD2018-52 IE2018-70 |
Tomoya Takiwaki, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
(53)
ICD |
09:50-10:15 |
A Ring-VCO Using Bootstrap Inverter CPM2018-92 ICD2018-53 IE2018-71 |
Akinori Yamamoto, Cong-Kha Pham (UEC) |
Fri, Dec 7 AM
09:00 - 10:15 |
(54)
VLD |
09:00-09:25 |
Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC VLD2018-65 DC2018-51 |
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(55)
VLD |
09:25-09:50 |
Flip-Flops with different retention characteristics for process variation estimation VLD2018-66 DC2018-52 |
Kento Fukazawa, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ.) |
(56)
VLD |
09:50-10:15 |
A study on estimating the degradation of critical path delay using replica sensors VLD2018-67 DC2018-53 |
Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Fri, Dec 7 AM
10:30 - 11:30 |
| (57) |
10:30-11:30 |
[Keynote Address]
Tensor Processing Unit: A processor for neural network designed by Google |
Kazunori Sato (Google) |
| |
11:30-12:30 |
Lunch Break ( 60 min. ) |
Fri, Dec 7 PM
12:30 - 13:30 |
| (58) |
12:30-13:30 |
[Keynote Address]
AI in medical imaging diagnosis VLD2018-68 CPM2018-93 ICD2018-54 IE2018-72 CPSY2018-39 DC2018-54 RECONF2018-45 |
Hiroshi Fujita (Gifu Univ.) |
| |
13:30-13:45 |
Break ( 15 min. ) |
Fri, Dec 7 PM
13:45 - 15:00 |
(59)
CPSY |
13:45-14:10 |
CPSY2018-40 |
|
| (60) |
14:10-14:35 |
|
(61)
CPSY |
14:35-15:00 |
An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit CPSY2018-41 |
Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima (NAIST) |
Fri, Dec 7 PM
13:45 - 15:00 |
(62)
ICD |
13:45-14:10 |
Autonomous SCM capacity adjustment method in SCM/NAND flash hybrid storage CPM2018-94 ICD2018-55 IE2018-73 |
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) |
(63)
ICD |
14:10-14:35 |
Ultra-long-term Measurement of Aging Degradation on Ring Oscillators by using FPGA and Micro Controller CPM2018-95 ICD2018-56 IE2018-74 |
Hiroki Nakano (KIT), Ryo Kishida (TUS), Jun Furuta, Kazutoshi Kobayashi (KIT) |
(64)
ICD |
14:35-15:00 |
Analysis of Conductive Power Noise Characteristics in Digital IC Chips between two Different IC Packaging Structures CPM2018-96 ICD2018-57 IE2018-75 |
Akihiro Tsukioka, Kosuke Jike, Koh Watanabe, Noriyuki Miura, Makoto Nagata (Kobe Univ.) |
Fri, Dec 7 PM
13:45 - 15:00 |
(65)
VLD |
13:45-14:10 |
A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process VLD2018-69 DC2018-55 |
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
(66)
VLD |
14:10-14:35 |
Process Variation-aware Model-based OPC using 0-1 Quadratic Programming VLD2018-70 DC2018-56 |
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) |
(67)
VLD |
14:35-15:00 |
Comparison of Machine Learning-Based Lithography Hotspot Detection Methods under Optimized Hyperparameters VLD2018-71 DC2018-57 |
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
| |
15:00-15:15 |
Break ( 15 min. ) |
Fri, Dec 7 PM
15:15 - 16:05 |
(68)
CPSY |
15:15-15:40 |
Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface CPSY2018-42 |
Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Hideharu Amano (Keio Univ.) |
(69)
CPSY |
15:40-16:05 |
. CPSY2018-43 |
Tomohiro Totoki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
Fri, Dec 7 PM
15:15 - 16:55 |
(70)
CPM |
15:15-15:40 |
Quarter Video Graphics Array Image Sensor with Linear and Wide-Dynamic-Range Output Developed by Pixel-Wise 3D Integration CPM2018-97 ICD2018-58 IE2018-76 |
Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto (Univ. of Tokyo) |
(71)
IE |
15:40-16:05 |
A 4-cell per Pixel Structure Image Sensor with Gradient-Based Motion Estimation Function CPM2018-98 ICD2018-59 IE2018-77 |
Tomohiro Aratani, Takayuki Hamamoto (TUS) |
(72)
IE |
16:05-16:30 |
A Method of Image Processing for Extraction of Plant Growth Indicators toward Development of Plant Growth Estimation Technologies CPM2018-99 ICD2018-60 IE2018-78 |
Yasunori Sakane, Takumi Okamoto, Tetsushi Koide (Hiroshima Univ.), Atsushi Ogawa, Masashi Komine, Chiharu Sone, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Yoshihiro Kaneta, Yukio Yaji, Yoshikazu Ishii (Akita Prefectural Univ.), Toshihiro Kasama, Wojciech Bula, Yoshishige Endo, Ryo Miyake (The Univ. of Tokyo) |
(73)
IE |
16:30-16:55 |
Non-Linear Signal Processing Super Resolution for 8K Endoscope Camera
-- Real-Time Super Resolution for 8K Endoscope -- CPM2018-100 ICD2018-61 IE2018-79 |
Chinatsu Mori, Seiichi Gohshi (Kogakuin Univ.), Kenkichi Tanioka (Medical Consotium), Hiromasa Yamashita (Kairos) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Koyo Nitta (NTT)
E- :  t        |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| CPM |
Technical Committee on Component Parts and Materials (CPM) [Latest Schedule]
|
| Contact Address |
|
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Takashi Hashimoto (Panasonic Corporation)
E-:      1967 pa  c |
| IE |
Technical Committee on Image Engineering (IE) [Latest Schedule]
|
| Contact Address |
Kei Kawamura (KDDI Research)
E-: ie- n 2017 |
| CPSY |
Technical Committee on Computer Systems (CPSY) [Latest Schedule]
|
| Contact Address |
Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-:   
CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/ |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
|
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Masato Motomura（Hokkaido Univ.）
E-:   ist   i |
| Announcement |
http://www.ieice.org/~reconf/ |
| IPSJ-ARC |
Special Interest Group on System Architecture (IPSJ-ARC) [Latest Schedule]
|
| Contact Address |
|
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Yukio Mitsuyama (Kochi Univ. of Tech.)
E-:    o - |
| Announcement |
Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/ |
| IPSJ-EMB |
Special Interest Group on Embedded Systems (IPSJ-EMB) [Latest Schedule]
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| Contact Address |
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Last modified: 2019-01-07 16:28:55
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