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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP | 2023-11-29 14:15 |
Okinawa | Nago city commerce and industry association | Reproduction of nonlinear dynamics of asthma delay model using ergodic sequential logic and efficient FPGA implementation Isaki Yamamoto, Hiroyuki Torikai (Hosei Univ.)  NLP2023-77 |
Lipopolysaccharides (LPS) present in the air and other media act as endotoxins when they enter blood vessels. Depending ... [more] | NLP2023-77 p.74 |
| MW, EMCJ, EST, IEE-EMC [detail] | 2023-10-20 15:50 |
Yamagata | Yamagata University (Primary: On-site, Secondary: Online) |
Transformation of circuit equations expressed by convolutional integrals with retarded electromagnetic coupling into neutral-type delayed differential equations Shuya Ehara, Takasi Hisakado, Mahfuzul Islam (Kyoto Univ) EMCJ2023-69 MW2023-123 EST2023-96 |
In this paper, as an extension of conventional concentrated constant circuits, circuit equations are derived by consider... [more] | EMCJ2023-69 MW2023-123 EST2023-96 pp.176-181 |
| RCS | 2023-06-16 09:30 |
Hokkaido | Hokkaido University, and online (Primary: On-site, Secondary: Online) |
Evaluation of Impact of Fractional Delay on Digital Self-Interference Cancellers in USRP-Based Full-Duplex Terminals Kaisei Yamamoto, Kazuki Komatsu (Toyohashi Univ. of Tech.), Yuichi Miyaji (Aichi Inst. of Tech.), Hideyuki Uehara (Toyohashi Univ. of Tech.) RCS2023-65 |
Time-domain cancellers assume that the received and reconstructed self-interference signals are perfectly time synchroni... [more] | RCS2023-65 pp.218-223 |
| DC | 2022-12-16 13:10 |
Yamaguchi | (Primary: On-site, Secondary: Online) |
On Improving the Accuracy of LSI Small Delay Fault Diagnosis Shinnosuke Fujita, Stefan Holst, Xiaoqing Wen (Kyutech) DC2022-72 |
With today's tight timing margins, increasing manufacturing variation, and the development of nanometer technology, timi... [more] | DC2022-72 pp.1-6 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:20 |
Kumamoto | (Primary: On-site, Secondary: Online) |
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 |
In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by... [more] | VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 pp.156-161 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| RCS, SR, SRW (Joint) |
2022-03-04 16:00 |
Online | Online | OFDM Wireless Receivers based on Time-to-Digital Conversion Yang Yang, Fukawa Kazuhiko, Chang Yuyuan (Tokyo Inst. of Tech.) RCS2021-292 |
To aim at low-cost OFDM wireless receivers with low-power, the report investigates a new analog-to-digital converter (AD... [more] | RCS2021-292 pp.201-206 |
| DC | 2022-03-01 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67 |
It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] | DC2021-67 pp.18-23 |
| DC | 2022-03-01 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73 |
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs．... [more] | DC2021-73 pp.51-56 |
| DC | 2022-03-01 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] | DC2021-74 pp.57-62 |
| DC | 2021-02-05 10:30 |
Online | Online | A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) DC2020-69 |
FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure pr... [more] | DC2020-69 pp.1-6 |
| DC | 2020-12-11 13:00 |
Hyogo | (Primary: On-site, Secondary: Online) |
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59 |
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] | DC2020-59 pp.1-6 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:30 |
Online | Online | Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 |
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] | VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 pp.12-17 |
| MBE, NC, NLP, CAS (Joint) [detail] |
2020-10-29 15:20 |
Online | Online | Unsupervised learning based on local interactions between reservoir and readout neurons Tstuki Kato, Satoshi Moriya, Hideaki Yamamoto, Masao Sakuraba, Shigeo Sato (Tohoku Univ.) NC2020-12 |
Reservoir computing is suitable for implementations in edge computing devices thanks to its low computational cost and e... [more] | NC2020-12 pp.21-23 |
| HWS, VLD [detail] | 2020-03-04 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning Kota Muroi, Yukihide Kohira (UoA) VLD2019-103 HWS2019-76 |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] | VLD2019-103 HWS2019-76 pp.53-58 |
| DC | 2019-12-20 16:30 |
Wakayama | Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85 |
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] | DC2019-85 pp.37-42 |
|
| MSS, CAS, SIP, VLD | 2019-07-31 10:00 |
Iwate | Iwate Univ. | Time Domain Analysis of Equivalent Circuit Model with Retardation by Delayed Differential Equations Daisuke Akimaru, Takashi Hisakado, Mahfuzul Islam, Osami Wada (Kyoto Univ.) CAS2019-13 VLD2019-19 SIP2019-29 MSS2019-13 |
In this paper, we formulate a circuit model of time domain including propagation delay of electromagnetic field. First,... [more] |
CAS2019-13 VLD2019-19 SIP2019-29 MSS2019-13 pp.55-60 |
| CPSY, DC, IPSJ-ARC [detail] | 2019-07-26 11:25 |
Hokkaido | Kitami Civic Hall | Inter-Node Direct Memory Access Performance with Distributed Switch for Full-Mesh Connection Between Accelerators with Optical Hub Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino (PETRA) CPSY2019-32 DC2019-32 |
In order to improve communication performance for paralle processing, we have proposed an optical hub that connects node... [more] | CPSY2019-32 DC2019-32 pp.171-176 |
| HWS, VLD | 2019-02-27 15:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Timing Correction by Constrained Temperature Dependent Clock Skew Mineo Kaneko (JAIST) VLD2018-103 HWS2018-66 |
This report treats temperature dependent clock skew scheduling for a general class of sequential circuits. Previous stud... [more] | VLD2018-103 HWS2018-66 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
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