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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)  VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| DC | 2022-03-01 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] | DC2021-74 pp.57-62 |
| DC | 2020-12-11 13:00 |
Hyogo | (Primary: On-site, Secondary: Online) |
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59 |
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] | DC2020-59 pp.1-6 |
| EST | 2020-01-31 09:30 |
Oita | Beppu International Convention Center | Worst Case Analysis of DME Tropospheric Propagation Delay Atsushi Kezuka, Kambayashi Atsushi, Takayuki Yoshihara, Naoki Fujii (ENRI) EST2019-90 |
RNP route implementations to busy airports are being planed to support aircraft navigation in EU, Japan and other countr... [more] | EST2019-90 pp.59-62 |
| DC | 2019-12-20 16:30 |
Wakayama | Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85 |
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] | DC2019-85 pp.37-42 |
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| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Study on the Applicability of ATPG Pattern for DFT Circuit Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44 |
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] | VLD2018-58 DC2018-44 pp.131-136 |
| DC | 2018-02-20 10:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79 |
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs. However, faulty TSVs may ... [more] |
DC2017-79 pp.13-18 |
| DC | 2017-02-21 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2016-78 |
This paper discusses delay-robustness of a four-phase dual-rail asynchronous system at register transfer level (RTL). A ... [more] | DC2016-78 pp.23-28 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. ... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An approach to LFSR/MISR seed generation for delay fault BIST Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66 |
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST. A widely used conventional way to... [more] |
VLD2015-70 DC2015-66 pp.213-218 |
| DC | 2015-02-13 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg | A Method of LFSR Seed Generation for Hierarchical BIST Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85 |
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST). In BIST, alth... [more] |
DC2014-85 pp.43-48 |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 08:55 |
Kagoshima | A Method of LFSR Seed Generation for Delay Fault BIST Taro Honda, Satoshi Ohtake (Oita Univ.) VLD2013-92 DC2013-58 |
In this paper, we propose a method to generate LFSR seeds for delay fault BIST. A conventional way to generate seeds is ... [more] | VLD2013-92 DC2013-58 pp.227-231 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:45 |
Kagoshima | A Method of High Quality Transition Test Generation Using RTL Information Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60 |
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] | VLD2013-94 DC2013-60 pp.239-244 |
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| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| DC | 2013-02-13 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] | DC2012-84 pp.25-30 |
| DC | 2012-06-22 13:00 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | An evaluation of a don't care filling method to improve fault sensitization coverage Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9 |
A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] | DC2012-9 pp.1-6 |
| DC | 2012-06-22 14:20 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | [Invited Talk]
Empirical study for signal integrity-defects Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima) DC2012-12 |
We try to empirically study signal integrity-defects. In this study, we analyze the resistive open fault that causes th... [more] |
DC2012-12 pp.21-26 |
| DC | 2012-02-13 11:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78 |
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] | DC2011-78 pp.13-18 |
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