Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2009-99
An Automatic Layout System for Timing Pulse Generator of Small LCD Driver Circuits
Shohei Asakawa, Yuichi Sakakibara, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo), Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota (Sharp Corp.)
pp. 1 - 6
VLD2009-100
Analog Macro Layout Generation Based on Regular Bulk Structure
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 7 - 12
VLD2009-101
Circuit Structure of Level Shifter for Sub-threshold Operation
Tomohiro Ishizaki, Satoshi Koyama, Kimiyoshi Usami (Shibaura Int. of Tech.)
pp. 13 - 18
VLD2009-102
A Delay Variation Modeling Algorithm with Considering Supply Voltage and Local Temperature
Hideki Yanagawa, Haruo Miki, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
pp. 19 - 24
VLD2009-103
Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors
Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST)
pp. 25 - 30
VLD2009-104
Variation-Tolerant Decomposition of MOS Transistor
Bo Liu, Atsushi Ochi, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 31 - 36
VLD2009-105
An efficient technique to search failure-areas for yield estimation via partial hyperspherephere
Takanori Date, Shiho Hagiwara, Kazuya Masu (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.)
pp. 37 - 42
VLD2009-106
[Invited Talk]
Changing Organization through Continuous Data Collection with Business Microscope
Koji Ara, Nobuo Sato, Kazuo Yano (Hitachi), Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda)
pp. 43 - 47
VLD2009-107
Study of Via Programmable Logic Device VPEX for wiring architecture and Logic Array Block
Shouta Yamada, Yuuichi Kokushou, Tomohiro Nishimoto, Naoyuki Yoshida, Ryohei Hori, Naoki Matsumoto, Tatsuya Kitamori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 49 - 54
VLD2009-108
Examination of the best basic logic gate architecture for Via programmable logic device
Ryohei Hori, Yuuichi Kokushou, Tomohiro Nishimoto, Shouta Yamada, Naoyuki Yoshida, Naoki Matsumoto, Takeshi Fujino (Ritsumei Univ.), Masaya Yoshikawa (Meijo Univ.)
pp. 55 - 60
VLD2009-109
Wiring delay of Logic Element used in Via programmable logic device VPEX
Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ)
pp. 61 - 66
VLD2009-110
High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
pp. 67 - 72
VLD2009-111
On an Accuracy Improvement of a Statistical Timing Analysis Using Gaussian Mixture Models
Atsutaka Obata, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.)
pp. 73 - 78
VLD2009-112
Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests
Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.)
pp. 79 - 83
VLD2009-113
Implementation Scheme for Power Gating and its Influence to Energy Reduction
Yuya Ohta, Satoshi Koyama, Tatsunori Hashida, Tetsuya Muto, Tatsuya Yamamoto, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 85 - 90
VLD2009-114
A Break Even Time Prediction of Run-Time Power Gating Circuits by an On-chip Leakage Monitor using an MTCMOS circuit
Satoshi Koyama, Tatsunori Hashida, Kimiyoshi Usami (Shibaura Inst. of Tech.), Daisuke Ikebuchi, Hideharu Amano (Keio Univ.)
pp. 91 - 96
VLD2009-115
Fast Estimation Method of Peak Power considered Input Vector and Inner State of a Circuit
Nobuyoshi Takahashi (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Yukihide Kohira (The Univ. of Aizu), Atsushi Takahashi (Osaka Univ.)
pp. 97 - 102
VLD2009-116
Analytical Evaluation of Average Switching Energy of Adders
Shinji Ohno, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
pp. 103 - 107
VLD2009-117
Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages
Masaki Kinoshita (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agr and Tech.), Atsushi Takahashi (Osaka Univ.)
pp. 109 - 114
VLD2009-118
Clock Distribution Optimization under Deskew
Mitsuhiro Yamaguchi, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 115 - 119
VLD2009-119
Clustering Method for Low Power Clock Tree in General Syncrhonous Framework
Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Osaka univ)
pp. 121 - 126
VLD2009-120
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors
Takahiro Kumura (NEC/Osaka Univ.), Soichiro Taga, Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 127 - 132
VLD2009-121
Performance evaluation of ADDER with Error-Detection-Correction Mechanism
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Inst. of Tech.), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ)
pp. 133 - 137
VLD2009-122
High-Level Design Conditions for Post-Fabrication Timing-Adjustable Datapaths
Akira Tehara, Mineo Kaneko (JAIST)
pp. 139 - 144
VLD2009-123
A Comparison of Two Approximate String Matching Algorithms Implemented on an FPGA
Keisuke Shimizu, Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
pp. 145 - 150
VLD2009-124
Estimating Signal Transition Frequency of Arithmetic Circuits Using Cell Delay Model
Hirotaka Kawashima, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
pp. 151 - 156
VLD2009-125
Circuit conversion for reducing false negatives on formal verification of sequential circuit
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.)
pp. 157 - 162
VLD2009-126
An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
pp. 163 - 168
VLD2009-127
Design and Implementation of an AMBA AHB Compliant Bus Architecture on FPGA
Xuan-Tu Tran, Hai-Phong Phan, Van-Huan Tran, Quang-Vinh Tran, Ngoc-Binh Nguyen (Vietnam National Univ.)
pp. 169 - 174
VLD2009-128
An ASIC implementation of a group signature algorithm using two-level behavioral synthesis
Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako (NEC)
pp. 175 - 180
VLD2009-129
A Design of an Adaptive Network on Chip for the Many-core System
Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)
pp. 181 - 186
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.