Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2010] | [2011] | [2012] | [2013] | [2014] | [2015] | [2016] | [Japanese] / [English]
VLD2013-61
A VLSI algorithm for computing correctly rounded hypotenuse
Hiroyuki Yataka, Naofumi Takagi (Kyoto Univ.)
pp. 1 - 6
VLD2013-62
Fast distance calculation method for rooted tree with CUDA
Hiroki Sakamoto, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 7 - 12
VLD2013-63
Adjacent Common Centroid Placement for Analog IC Layout Design
Kenichiro Murotatsu, Kunihiro Fujiyoshi (TUAT)
pp. 13 - 18
VLD2013-64
An Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips
Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan University Univ.), Tsung-Yi Ho (National Cheng Kung Univ.)
pp. 19 - 24
VLD2013-65
A Heuristic Design Method for Yield Improvement based on PPCs
Shunichi Sanae, Yuko Hara-Azumi (NAIST), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST)
pp. 27 - 32
VLD2013-66
Fault-Tolerant Design with Less Overhead than DMR
Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 33 - 37
VLD2013-67
Suspicious timing error prediction using check points
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 39 - 44
VLD2013-68
A controller design in high-level synthesis for multi-cycle transient fault tolerance
Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 45 - 50
VLD2013-69
A Hardware/Software Simulator for NoC using SystemC and QEMU
Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 63 - 68
VLD2013-70
Improved via programmable structured ASIC VPEX3S
-- Improvement of basic logic element to improve operation speed --
Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 75 - 80
VLD2013-71
New Via Programmable Architecture VPEX4 (1)
-- Development of new logic element for improvement of routability and power consumption --
Ryohei Hori, Taku Otani, Tatsuro Hitomi, Shota Ueguchi (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 81 - 86
VLD2013-72
Evaluation of Via Programmable Device named VPEX using benchmark circuits
Shota Ueguchi, Ryohei Hori, Taku Otani (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 87 - 92
VLD2013-73
[Invited Talk]
Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi)
pp. 93 - 96
VLD2013-74
[Invited Talk]
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)
pp. 97 - 100
VLD2013-75
[Invited Talk]
Cu Wiring Technology for 3D/2.5D Packaging
Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.)
pp. 101 - 106
VLD2013-76
[Invited Talk]
Chip Thinning Technologies for Chip Stacking Packages
Shinya Takyu, Tetsuya Kurosawa (Toshiba)
pp. 107 - 112
VLD2013-77
System-level design method considering the interrupt processing
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
pp. 119 - 124
VLD2013-78
Function-Level Profiling for Embedded Software with QEMU
Tran Van Dung, Ittetsu Taniguchi (Ritsumeikan Univ.), Takuji Hieda (Kyushu Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 125 - 128
VLD2013-79
An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 129 - 134
VLD2013-80
Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo)
pp. 135 - 140
VLD2013-81
Energy evaluation of writing reduction method for non-volatile memory
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 141 - 146
VLD2013-82
Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers
Yudai Itoi, Shinji Kimura (Waseda Univ.)
pp. 147 - 152
VLD2013-83
Evaluations of Variations on Ring Oscillators from Plasma Induced Damage in Bulk and SOTB Processes
Ryo Kishida, Michitarou Yabuuchi, Azusa Oshima, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
pp. 159 - 164
VLD2013-84
A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs
Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.)
pp. 165 - 170
VLD2013-85
An inverter block construction method to reduce test data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute)
pp. 171 - 176
VLD2013-86
[Keynote Address]
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"
Osamu Mori (JAXA)
pp. 177 - 181
VLD2013-87
[Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)
p. 183
VLD2013-88
On Synthesis Algorithm for Parallel Index Generator Units
Yusuke Matsunaga (Kyushu Univ.)
pp. 203 - 208
VLD2013-89
A thermal analysis algorithm for VLSI chip by GPGPU
Takashi Ohmura, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.)
pp. 209 - 214
VLD2013-90
List Scheduling Algorithms for Task Graphs with Data Parallelism
Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, Lin Meng (Ritsumeikan Univ.)
pp. 215 - 220
VLD2013-91
A Study of Burn-In Test Prediction by Data Mining
Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics)
pp. 221 - 226
VLD2013-92
A Method of LFSR Seed Generation for Delay Fault BIST
Taro Honda, Satoshi Ohtake (Oita Univ.)
pp. 227 - 231
VLD2013-93
Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.)
pp. 233 - 238
VLD2013-94
A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.)
pp. 239 - 244
VLD2013-95
Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis
Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.)
pp. 245 - 249
VLD2013-96
Estimation for Method of Controller Implementation in High-Level Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 257 - 262
VLD2013-97
Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 263 - 268
VLD2013-98
Scheduling of PDE Setting and Timing Test for Post Silicon Skew Tuning
Mineo Kaneko (JAIST)
pp. 269 - 274
VLD2013-99
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
pp. 275 - 280
VLD2013-100
A Method and Evaluation of Dynamic Relocation for Shared Multi-FPGA System
Yuta Ukon, Takuya Otsuka, Takashi Aoki, Yusuke Sekihara, Akihiko Miyazaki (NTT)
pp. 281 - 286
VLD2013-101
A Study on the Design of Processor System for Stream Processing
Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT)
pp. 287 - 292
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.