Online edition: ISSN 2432-6380
[TOP] | [2018] | [2019] | [2020] | [2021] | [2022] | [2023] | [2024] | [Japanese] / [English]
DC2021-23
Soft Errors on Flip-flops Depending on Circuit and Layout Structures Estimated by TCAD Simulations
Moeka Kotani, Ryuichi Nakajima (KIT), Kazuya Ioki (ROHM), Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 1 - 6
DC2021-24
Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices
Kenji Mii, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ.)
pp. 7 - 12
DC2021-25
MTJ-based non-volatile SRAM circuit with data-aware store control for energy saving
Hisato Miyauchi, Kimiyoshi Usami (SIT)
pp. 13 - 18
DC2021-26
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS)
pp. 19 - 24
DC2021-27
Block Sparse MLP-based Vision DNN Accelerators on Embedded FPGAs
Akira Jinguji, Hiroki Nakahara (Tokyo Tech)
pp. 25 - 30
DC2021-28
Sparsity-Gradient-Based Pruning and the Vitis-AI Implementation for Compacting Deep Learning Models
Hengyi Li, Xuebin Yue, Lin Meng (Ritsumeikan Univ.)
pp. 31 - 36
DC2021-29
A Multilayer Perceptron Training Accelerator using Systolic Array
Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Toyko Tech)
pp. 37 - 42
DC2021-30
Basic evaluation of ReNA, a DNN accelerator using numerical representation posit
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.)
pp. 43 - 48
DC2021-31
Low power neural network by reducing the operating voltage of SRAM
Keisuke Kozu, Kazuteru Namba (Chiba Univ.)
pp. 49 - 53
DC2021-32
Triple-Rail Stochastic Number and Its Applications
Shoki Kawaminami, Shigeru Yamashita (Ritsumeikan Univ)
pp. 54 - 59
DC2021-33
Improving Accuracy of Addition for Stochastic Computing
Ichilawa Katsuhiro, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 60 - 65
DC2021-34
Error Recovery Method by Canceling Errors on DMFBs
Yuji Wada, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 66 - 71
DC2021-35
Determining Optimal Number of Layers for Network-Flow-based Sample Preparation
Akira Ishida, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 72 - 77
DC2021-36
A Dual-mode SAR ADC to Detect Power Analysis Attack
Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.)
pp. 78 - 82
DC2021-37
Diagnosis of Switching-Induced IR Drop by On-Chip Voltage Monitors
Kazuki (Kobe Univ.), Leonidas Kataselas (Aristotle Univ.), Ferenc Fodor (IMEC), Alkis Hatzopoulos (Aristotle Univ.), Makoto Nagata (Kobe Univ.), Erik Jan Marinissen (IMEC)
pp. 83 - 86
DC2021-38
Development of Spiking Neural Network with Mem Capacitor
-- Reduction of recognition accuracy loss by improving the conversion method between synaptic strength and capacitance --
Atsushi Sawada, Reon Oshio, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima (NAIST)
pp. 87 - 92
DC2021-39
Routing of Delivery Drones with Load- and Wind-Dependent Flight Speed
Satoshi Ito, Keishi Akaiwa, Yusuke Funabashi, Hiroki Nishikawa, Xiangbo Kong (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 93 - 98
DC2021-40
Design Method of ECG Measurement System Using Compression Sensing
Yuki Matsumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ)
pp. 99 - 104
DC2021-41
Calculation method of correctly rounded exponential function on an FPGA
Takuya Haraguchi, Naofumi Takagi (Kyoto Univ.)
pp. 105 - 110
DC2021-42
The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
pp. 111 - 116
DC2021-43
Development of specific cache memory for Hybrid Graph Traversal Algorithm
Yushi Haraguchi, Kazuya Tanigawa (HCU), Kentarou Sano (RIKEN), Tetsuo Hironaka (HCU)
pp. 117 - 122
DC2021-44
A real-time exercise data recording system with an FPGA for fitness games
Jun Takigawa, Tetsu Narumi (UEC)
pp. 123 - 127
DC2021-45
Transition of R & D themes in Design Gaia
-- Analysis by text mining --
Tadashi Okabe (TIRI)
pp. 128 - 132
DC2021-46
(See Japanese page.)
pp. 133 - 138
DC2021-47
Performance comparison of high-level synthesis tools using the gravitational many-body problem
-- On the difference between SDSoC and Vitis --
Akio Muramatsu, Tetsu Narumi (UEC)
pp. 139 - 143
DC2021-48
Wafer-level Variation Modeling for Multi-site Testing of RF Circuits
Riaz-ul-haque Mian (Shimane Univ.), Michihiro Shintani (NAIST)
pp. 144 - 149
DC2021-49
Extension of Channel Routing Method for Two-Layer Routing Problem including inside Terminals
Kaito Ishigami, Kunihiro Fujiyoshi (TUAT)
pp. 150 - 155
DC2021-50
An Improved Method of Layout Pattern Classification with Creating Representative Clip
Tomoya Masutani, Ishino Shuhei, Kunihiro Fujiyoshi (TUAT)
pp. 156 - 161
DC2021-51
Mask Optimization Method Using Simulated Quantum Annealing
Yukihide Kohira, Haruki Nakayama, Naoki Nonaka (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA Corporation)
pp. 162 - 167
DC2021-52
Convolutional Neural Network using RISC-V
Koki Oshiro (UEC)
pp. 168 - 171
DC2021-53
Operating-Condition-Aware Power-Gating-Switch Control Technique and Its Application to Nonvolatile Logic LSI
Fangcen Zhong, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)
pp. 172 - 177
DC2021-54
A Sub uW and 14bit Resolution Temperature Sensor for IoT Using Thermistor-Defined TDC
Nguyen Trong Hung (UEC), Van Trung Nguyen (LQDTU), Koichiro Ishibashi (UEC)
pp. 178 - 181
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.