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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Maximum power estimator for ultra-low power energy harvesters Takanori Sato, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)  ICD2016-86 CPSY2016-92 |
This paper proposes a maximum power estimator (MPE) for low-power energy harvesting. The proposed circuit measures an o... [more] |
ICD2016-86 CPSY2016-92 p.105 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Low-current, high-speed switched-capacitor amplifier with adaptive biasing technique Kazuki Takegawa, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2016-87 CPSY2016-93 |
This paper proposes a switched-capacitor amplifier with adaptive biasing technique. The proposed amplifier employs adapt... [more] | ICD2016-87 CPSY2016-93 p.107 |
| ICD, SDM | 2014-08-05 10:25 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | Development of a Low Standby Power, Six-Transistor CMOS SRAM Employing a Single Power Supply Ryusuke Ito (Chuo Univ.), Nobuaki Kobayashi (NUT), Tadayoshi Enomoto (Chuo Univ.) SDM2014-73 ICD2014-42 |
We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand b... [more] | SDM2014-73 ICD2014-42 pp.59-64 |
| ICD | 2010-04-22 15:20 |
Kanagawa | Shonan Institute of Tech. | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 |
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] | ICD2010-9 pp.47-52 |
| PN, OPE, EMT, LQE | 2009-01-30 10:40 |
Kyoto | Kyoto Institute Technology (Matsugasaki Campus) | Dissipation in Artificial Dielectrics Makoto Furuta, Kazuki Namikoshi, Ikuo Awai (Ryukoku Univ.) PN2008-75 OPE2008-178 LQE2008-175 |
It is clarified that there are two dissipation schemes in the artificial dielectrics, the polarizing current and circula... [more] | PN2008-75 OPE2008-178 LQE2008-175 pp.179-184 |
| VLD, ICD | 2008-03-06 16:35 |
Okinawa | TiRuRu | Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178 |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] | VLD2007-155 ICD2007-178 pp.67-72 |
| DC | 2008-02-08 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Current dissipation of Test pattern generators using ATPG vectors Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa (Tokai univ.) DC2007-80 |
Recently, the operating speed of LSI is more fast and the scale of LSI is more larger. These induce increasing the dissi... [more] | DC2007-80 pp.83-88 |
| ICD, ITE-CE | 2007-12-13 16:50 |
Kochi | A Low Dynamic Power and Low Leakage Power 90-nm CMOS SRAM with Wide Operating Margin Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) ICD2007-127 |
A large “write” operating margin, low-power, low leakage power 90-nm CMOS 2K-bit SRAM was fabricated incorporating a new... [more] | ICD2007-127 pp.41-46 |
|
| CPM, ED, LQE | 2007-10-12 09:50 |
Fukui | Fukui Univ. | Low leakage current ITO schottky electrode for AlGaN/GaN HEMT Keita Matsuda, Takeshi Kawasaki, Ken Nakata, Takeshi Igarashi, Seiji Yaegashi (Eudyna Devices) ED2007-167 CPM2007-93 LQE2007-68 |
AlGaN/GaN HEMTs are attractive devices for high power switching applications because of their high electron mobility and... [more] | ED2007-167 CPM2007-93 LQE2007-68 pp.57-61 |
| ICD, SIP, IE, IPSJ-SLDM | 2006-10-27 10:50 |
Miyagi | Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET Shigeyoshi Watanabe, Masaki Kanai, Akira Nagasawa, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of dual... [more] | SIP2006-106 ICD2006-132 IE2006-84 pp.31-36 |
|
| ICD | 2006-04-13 10:45 |
Oita | Oita University | [Special Invited Talk]
Sub-1V DRAM Design Takayuki Kawahara (Hitachi Central Research Lab.) |
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,... [more] | ICD2006-4 pp.19-24 |
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