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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Vice Chair Yuichi Sakurai (Hitachi)
Secretary Yukihiro Sasagawa (Socionext), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Hardware Security (HWS) [schedule] [select]
Chair Daisuke Suzuki (Mitsubishi Electric)
Vice Chair Yuichi Hayashi (NAIST), Toru Akishita (Sony Semiconductor Solutions)
Secretary Hirotake Yamamotoi (Sony Semiconductor Solutions), Junichi Sakamoto (AIST)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Makoto Ikeda (Univ. of Tokyo)
Vice Chair Hayato Wakabayashi (Sony Semiconductor Solutions)
Secretary Yoshiaki Yoshihara (Kioxia), Kosuke Miyaji (Shinshu Univ.)
Assistant Ryo Shirai (Kyoto Univ.), Jun Shiomi (Osaka Univ.), Takeshi Kuboki (Sony Semiconductor Solutions)

Conference Date Wed, Feb 28, 2024 14:00 - 17:10
Thu, Feb 29, 2024 09:20 - 17:10
Fri, Mar 1, 2024 09:20 - 17:10
Sat, Mar 2, 2024 09:20 - 12:30
Topics  
Conference Place Tiruru 
Address 3-11-1 Nishi, Naha-shi, Okinawa, 900-0036, Japan
Transportation Guide https://www.tiruru.or.jp/
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, HWS, ICD.

Wed, Feb 28 PM  【VLD】
14:00 - 15:15
(1) 14:00-14:25 VLD2023-99 HWS2023-59 ICD2023-88 Masashi Tawada, Nozomu Togawa (Waseda Univ.)
(2) 14:25-14:50 Set-Pair Routing Solver with Layer-by-layer Formulation on ILP VLD2023-100 HWS2023-60 ICD2023-89 Yasuhiro Takashima (Univ of Kitakyushu)
(3) 14:50-15:15 High Level Datapath Synthesis for Enhanced Timing Tunability VLD2023-101 HWS2023-61 ICD2023-90 Mineo Kaneko (JAIST)
  15:15-15:30 Break ( 15 min. )
Wed, Feb 28 PM  【VLD】
15:30 - 17:10
(4) 15:30-15:55 A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem VLD2023-102 HWS2023-62 ICD2023-91 Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (JEDAT)
(5) 15:55-16:20 Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides VLD2023-103 HWS2023-63 ICD2023-92 Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat)
(6) 16:20-16:45 Single Trunk Routing Problem for Generalized Channel VLD2023-104 HWS2023-64 ICD2023-93 Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi (Tokyo Tech)
(7) 16:45-17:10 Research on Routing Method for Spacer-Is-Metal Type Self-Aligned Double Patterning VLD2023-105 HWS2023-65 ICD2023-94 Koki Tanaka, Takuto Amari, Kunihiro Fujiyoshi (TUAT)
Thu, Feb 29 AM  【VLD】
09:20 - 11:00
(8) 09:20-09:45 A Scalable Mapping Method for Elastic CGRAs VLD2023-106 HWS2023-66 ICD2023-95 Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT)
(9) 09:45-10:10 Instruction-set Extension Using Graph Neural Networks VLD2023-107 HWS2023-67 ICD2023-96 Ayumi Uki, Yuko Hara (TiTech)
(10) 10:10-10:35 VLD2023-108 HWS2023-68 ICD2023-97 ()
(11) 10:35-11:00 Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement VLD2023-109 HWS2023-69 ICD2023-98 Takahiro Kanamori, Songxiang Wang, Kimiyoshi Usami (SIT)
  11:00-11:15 Break ( 15 min. )
Thu, Feb 29 AM  【ICD】
11:15 - 12:30
(12) 11:15-11:40 Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration VLD2023-110 HWS2023-70 ICD2023-99 Jiyuan Xin, Makoto Ikeda (UTokyo)
(13) 11:40-12:05 A Study of Edge AI & Distributed DB Computing Architecture for Edge-Centric Digital Twin VLD2023-111 HWS2023-71 ICD2023-100 Hiroshi Miyata (TAN), Kazutami Arimoto (Okayama Pref. Univ.), Atsushi Hayami, Hisayoshi Mizuno (TAN), Tomoyuki Yokogawa (Okayama Pref. Univ.)
(14) 12:05-12:30 VLD2023-112 HWS2023-72 ICD2023-101 Shuhei Yokota, Rikuu Hasegawa, Kazuki Monta, Takaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univercity)
  12:30-14:00 Lunch Break ( 90 min. )
Thu, Feb 29 PM  【HWS】
14:00 - 15:15
(15) 14:00-14:25 Nano Artifact Metric Systems Resistant Against Clones Produced by Scanning Probe Lithography VLD2023-113 HWS2023-73 ICD2023-102 Akira Iwahashi, Naoki Yoshida, Katsunari Yoshioka (YNU), Tsutomu Matsumoto (AIST)
(16) 14:25-14:50 Fundamental study on individual identification using electromagnetic characteristics unique to electronic devices VLD2023-114 HWS2023-74 ICD2023-103 Tsuyoshi Kobayashi, Mio Akahori, Takahiro Horiguchi (Mitsubishi Electric)
(17) 14:50-15:15 VLD2023-115 HWS2023-75 ICD2023-104
  15:15-15:30 Break ( 15 min. )
Thu, Feb 29 PM  【VLD】
15:30 - 17:10
(18) 15:30-15:55 [Memorial Lecture]
Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits VLD2023-116 HWS2023-76 ICD2023-105
Kunihiro Oshima (Kyoto Univ.), Kazunori Kuribara (AIST), Takashi Sato (Kyoto Univ.)
(19) 15:55-16:20 [Memorial Lecture]
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits VLD2023-117 HWS2023-77 ICD2023-106
Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ.)
(20) 16:20-16:45 [Memorial Lecture]
Logic Locking over TFHE for Securing User Data and Algorithms VLD2023-118 HWS2023-78 ICD2023-107
Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto (Kyoto Univ.)
(21) 16:45-17:10 [Memorial Lecture]
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow VLD2023-119 HWS2023-79 ICD2023-108
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Tech)
Fri, Mar 1 AM  【VLD】
09:20 - 10:35
(22) 09:20-09:45 VLD2023-120 HWS2023-80 ICD2023-109 Kei Nakao, Yukihide Kohira, Hiroshi Saito, Yoichi Tomioka (Univ. of Aizu)
(23) 09:45-10:10 VLD2023-121 HWS2023-81 ICD2023-110
(24) 10:10-10:35 Fault Detectable Convolutional Neural Network Circuits With Dual Modular Redundancy Based on Mixed-precision Quantization VLD2023-122 HWS2023-82 ICD2023-111 Yamato Saikawa, Yuta Owada, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira (UoA)
  10:35-10:50 Break ( 15 min. )
Fri, Mar 1 AM  【HWS】
10:50 - 12:30
(25) 10:50-11:15 Pseudo-random Number Generator Design Robust against Fault Injection Attacks VLD2023-123 HWS2023-83 ICD2023-112 Sota Kado, Mingyu Yang, Yuko Hara (Tokyo Tech)
(26) 11:15-11:40 Investigation of electromagnetic irradiation noise reduction by on-chip LDOs VLD2023-124 HWS2023-84 ICD2023-113 Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.)
(27) 11:40-12:05 Improved Ring Oscillator Sensor for Laser Fault Injection Detection on FPGA VLD2023-125 HWS2023-85 ICD2023-114 Masaki Chikano (YNU), Shungo Hayashi, Junichi Sakamoto (YNU/AIST), Tsutomu Matsumoto (YNU)
(28) 12:05-12:30 Security Evaluation of Fault Analysis for SuperSonic VLD2023-126 HWS2023-86 ICD2023-115 Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
  12:30-14:00 Lunch Break ( 90 min. )
Fri, Mar 1 PM  【VLD】
14:00 - 15:15
(29) 14:00-14:25 High-Level Synthesis Method for Python Considering Runtime Profiling VLD2023-127 HWS2023-87 ICD2023-116 Yusuke Suzuki, Makoto Ikeda (UTokyo)
(30) 14:25-14:50 Modeling of Thin-Film Ferroelectric Memcapacitors Based on Gaussian Process Regression and its evaluation VLD2023-128 HWS2023-88 ICD2023-117 Ryoga Urata (KIT), Taiyo Shinoda, Mutsumi Kimura (Ryukoku Univ.), Michihiro Shintani (KIT)
(31) 14:50-15:15 Defect Coverage Estimation by Sampling in Testing Power TSV VLD2023-129 HWS2023-89 ICD2023-118 Koutaro Hachiya, Yudai Kawakami (THU)
  15:15-15:30 Break ( 15 min. )
Fri, Mar 1 PM  【HWS】
15:30 - 17:10
(32) 15:30-15:55 A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium VLD2023-130 HWS2023-90 ICD2023-119 Pengfei Sun, Makoto Ikeda (Tokyo Univ.)
(33) 15:55-16:20 Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203 VLD2023-131 HWS2023-91 ICD2023-120 Yuto Nakamura, Makoto Ikeda (UTokyo)
(34) 16:20-16:45 An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation VLD2023-132 HWS2023-92 ICD2023-121 Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo)
(35) 16:45-17:10 A Study on Post-Quantum Signature QR-UOV Hardware VLD2023-133 HWS2023-93 ICD2023-122 Hiroshi Amagasa, Rei Ueno (Tohoku Univ.), Kimihiro Yamakoshi, Kouha Kinjo, Rika Akiyama (NTT), Naofumi Homma (Tohoku Univ.)
Sat, Mar 2 AM  【HWS】
09:20 - 10:35
(36) 09:20-09:45 Countermeasure on AI Hardware against Adversarial Examples VLD2023-134 HWS2023-94 ICD2023-123 Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(37) 09:45-10:10 Demonstrating a Real Car Covered with Infra-red-cut Films to Hide itself from LiDAR VLD2023-135 HWS2023-95 ICD2023-124 Yuki Fukatsu, Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU)
(38) 10:10-10:35 Feasibility Study of Instrumentation Security for Infrastructure Monitoring Camera VLD2023-136 HWS2023-96 ICD2023-125 Nagisa Nishimura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.)
  10:35-10:50 Break ( 15 min. )
Sat, Mar 2 AM  【HWS】
10:50 - 12:30
(39) 10:50-11:15 Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography VLD2023-137 HWS2023-97 ICD2023-126 Kosei Nakamura, Makoto Ikeda (UT)
(40) 11:15-11:40 Composable Security in High Level Synthesis for Cipher Circuit Implementation VLD2023-138 HWS2023-98 ICD2023-127 Mingyu Yang, Gento Hiruma (Titech), Kazuo Sakiyama, Yang Li (UEC), Yuko Hara-Azumi (Titech)
(41) 11:40-12:05 eFPGA-based IP Protection of Embedded Processor Design VLD2023-139 HWS2023-99 ICD2023-128 Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara (Tokyo Tech)
(42) 12:05-12:30 A Study on formal verification of GF(2^m) arithmetic circuits including states VLD2023-140 HWS2023-100 ICD2023-129 Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E--mail: bi-u 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
HWS Technical Committee on Hardware Security (HWS)   [Latest Schedule]
Contact Address Junichi Sakamoto (AIST), Hirotake Yamamoto (SSS)
E--mail:hws-c 
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Yoshiaki Yoshihara (Kioxia)
E---mail: aoxia 


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