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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2024-02-28 15:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Locating High Power Consuming Area by Branch and Reconvergence Topology Analysis for Logic Circuit Tomoya Yamashita, Kohei Miyase, Xiaoqing Wen (Kyutech)  DC2023-101 |
In recent years, there has been remarkable progress in the manufacturing technology of LSIs (Large Scale Integration). D... [more] | DC2023-101 pp.41-46 |
| DC | 2023-02-28 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg (Primary: On-site, Secondary: Online) |
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuit Taiki Utsunomiya, Kohei Miyase, Ryu Hoshino (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2022-92 |
High power consumption in LSI testing may cause excessive IR-drop. When IR-drop becomes excessive, it causes excessive d... [more] | DC2022-92 pp.56-61 |
| DC | 2022-03-01 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73 |
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs．... [more] | DC2021-73 pp.51-56 |
| DC | 2021-02-05 12:00 |
Online | Online | Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2020-72 |
[more] | DC2020-72 pp.18-23 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:30 |
Online | Online | Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 |
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] | VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 pp.12-17 |
| DC | 2020-02-26 14:35 |
Tokyo | Power Analysis for Logic Area of LSI Including Memory Area Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93 |
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] | DC2019-93 pp.43-48 |
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| DC | 2020-02-26 15:00 |
Tokyo | Improving Controllability of Signal Transitions in the High Switching Area of LSI Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94 |
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] | DC2019-94 pp.49-54 |
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| DC | 2019-02-27 10:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Analysis of the hotspot distribution in the LSI Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74 |
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] | DC2018-74 pp.19-24 |
| DC | 2018-02-20 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Locating Hot Spots with Justification Techniques in a Layout Design Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80 |
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] | DC2017-80 pp.19-24 |
| DC | 2017-02-21 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75 |
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI techn... [more] | DC2016-75 pp.7-10 |
| DC | 2015-06-16 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method to Identify High Test Power Areas in Layout Design Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2015-18 |
The problems related to power consumption during at-speed testing is becoming more serious. Particularly, excessive peak... [more] | DC2015-18 pp.13-18 |
| DC | 2014-06-20 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A X-Filling Method for Low-Capture-Power Scan Test Generation Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12 |
In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activ... [more] |
DC2014-12 pp.15-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Method to Estimate the Number of Don't-Care Bits with Netlist Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) VLD2012-104 DC2012-70 |
X-filling is often utilized so as to achieve test compression, test power reduction, or test quality improvement etc. i... [more] |
VLD2012-104 DC2012-70 pp.261-266 |
| DC | 2012-06-22 15:45 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | An Evaluation of Low Power BIST Method Yasuo Sato, Senling Wang, Takaaki Kato, Kohei Miyase, Seiji Kajihara (Kyutech) DC2012-14 |
Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophi... [more] | DC2012-14 pp.33-38 |
| DC | 2012-02-13 11:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78 |
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] | DC2011-78 pp.13-18 |
| DC | 2012-02-13 11:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method to reduce shift-toggle rate for low power BIST Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) DC2011-80 |
Logic BIST using scan design has a problem with high power dissipation during test. In this work we propose a method tha... [more] | DC2011-80 pp.25-29 |
| DC | 2012-02-13 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Evaluation of a thermal and voltage estimation circuit for field test Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) DC2011-86 |
High dependability is required for an embedded system VLSI. High functionality and high performance of VLSI, due to the ... [more] | DC2011-86 pp.61-66 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:05 |
Miyazaki | NewWelCity Miyazaki | Capture power reduction in multi-cycle test structure Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) VLD2011-83 DC2011-59 |
Power consumption during Built-In Self-Test(BIST) is far larger than that of normal operation. Therefore, it may lead to... [more] | VLD2011-83 DC2011-59 pp.179-183 |
| DC | 2011-06-24 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13 |
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] | DC2011-13 pp.29-34 |
| DC | 2011-02-14 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60 |
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] | DC2010-60 pp.7-12 |
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