Online edition: ISSN 2432-6380
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HWS2023-59
Masashi Tawada, Nozomu Togawa (Waseda Univ.)
pp. 1 - 5
HWS2023-60
Set-Pair Routing Solver with Layer-by-layer Formulation on ILP
Yasuhiro Takashima (Univ of Kitakyushu)
pp. 6 - 11
HWS2023-61
High Level Datapath Synthesis for Enhanced Timing Tunability
Mineo Kaneko (JAIST)
pp. 12 - 17
HWS2023-62
A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (JEDAT)
pp. 18 - 23
HWS2023-63
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat)
pp. 24 - 29
HWS2023-64
Single Trunk Routing Problem for Generalized Channel
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi (Tokyo Tech)
pp. 30 - 35
HWS2023-65
Research on Routing Method for Spacer-Is-Metal Type Self-Aligned Double Patterning
Koki Tanaka, Takuto Amari, Kunihiro Fujiyoshi (TUAT)
pp. 36 - 41
HWS2023-66
A Scalable Mapping Method for Elastic CGRAs
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT)
pp. 42 - 47
HWS2023-67
Instruction-set Extension Using Graph Neural Networks
Ayumi Uki, Yuko Hara (TiTech)
pp. 48 - 53
HWS2023-69
Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement
Takahiro Kanamori, Songxiang Wang, Kimiyoshi Usami (SIT)
pp. 60 - 65
HWS2023-70
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration
Jiyuan Xin, Makoto Ikeda (UTokyo)
pp. 66 - 71
HWS2023-71
A Study of Edge AI & Distributed DB Computing Architecture for Edge-Centric Digital Twin
Hiroshi Miyata (TAN), Kazutami Arimoto (Okayama Pref. Univ.), Atsushi Hayami, Hisayoshi Mizuno (TAN), Tomoyuki Yokogawa (Okayama Pref. Univ.)
pp. 72 - 76
HWS2023-72
Shuhei Yokota, Rikuu Hasegawa, Kazuki Monta, Takaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univercity)
pp. 77 - 82
HWS2023-73
Nano Artifact Metric Systems Resistant Against Clones Produced by Scanning Probe Lithography
Akira Iwahashi, Naoki Yoshida, Katsunari Yoshioka (YNU), Tsutomu Matsumoto (AIST)
pp. 83 - 88
HWS2023-74
Fundamental study on individual identification using electromagnetic characteristics unique to electronic devices
Tsuyoshi Kobayashi, Mio Akahori, Takahiro Horiguchi (Mitsubishi Electric)
pp. 89 - 93
HWS2023-75
(See Japanese page.)
pp. 94 - 97
HWS2023-76
[Memorial Lecture]
Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits
Kunihiro Oshima (Kyoto Univ.), Kazunori Kuribara (AIST), Takashi Sato (Kyoto Univ.)
p. 98
HWS2023-77
[Memorial Lecture]
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits
Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ.)
p. 99
HWS2023-78
[Memorial Lecture]
Logic Locking over TFHE for Securing User Data and Algorithms
Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto (Kyoto Univ.)
p. 100
HWS2023-79
[Memorial Lecture]
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Tech)
pp. 101 - 106
HWS2023-80
Kei Nakao, Yukihide Kohira, Hiroshi Saito, Yoichi Tomioka (Univ. of Aizu)
pp. 107 - 112
HWS2023-81
(See Japanese page.)
pp. 113 - 118
HWS2023-82
Fault Detectable Convolutional Neural Network Circuits With Dual Modular Redundancy Based on Mixed-precision Quantization
Yamato Saikawa, Yuta Owada, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira (UoA)
pp. 119 - 124
HWS2023-83
Pseudo-random Number Generator Design Robust against Fault Injection Attacks
Sota Kado, Mingyu Yang, Yuko Hara (Tokyo Tech)
pp. 125 - 130
HWS2023-84
Investigation of electromagnetic irradiation noise reduction by on-chip LDOs
Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.)
pp. 131 - 134
HWS2023-85
Improved Ring Oscillator Sensor for Laser Fault Injection Detection on FPGA
Masaki Chikano (YNU), Shungo Hayashi, Junichi Sakamoto (YNU/AIST), Tsutomu Matsumoto (YNU)
pp. 135 - 140
HWS2023-86
Security Evaluation of Fault Analysis for SuperSonic
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 141 - 144
HWS2023-87
High-Level Synthesis Method for Python Considering Runtime Profiling
Yusuke Suzuki, Makoto Ikeda (UTokyo)
pp. 145 - 150
HWS2023-88
Modeling of Thin-Film Ferroelectric Memcapacitors Based on Gaussian Process Regression and its evaluation
Ryoga Urata (KIT), Taiyo Shinoda, Mutsumi Kimura (Ryukoku Univ.), Michihiro Shintani (KIT)
pp. 151 - 156
HWS2023-89
Defect Coverage Estimation by Sampling in Testing Power TSV
Koutaro Hachiya, Yudai Kawakami (THU)
pp. 157 - 160
HWS2023-90
A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium
Pengfei Sun, Makoto Ikeda (Tokyo Univ.)
pp. 161 - 166
HWS2023-91
Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203
Yuto Nakamura, Makoto Ikeda (UTokyo)
pp. 167 - 172
HWS2023-92
An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation
Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo)
pp. 173 - 177
HWS2023-93
A Study on Post-Quantum Signature QR-UOV Hardware
Hiroshi Amagasa, Rei Ueno (Tohoku Univ.), Kimihiro Yamakoshi, Kouha Kinjo, Rika Akiyama (NTT), Naofumi Homma (Tohoku Univ.)
pp. 178 - 183
HWS2023-94
Countermeasure on AI Hardware against Adversarial Examples
Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 184 - 189
HWS2023-95
Demonstrating a Real Car Covered with Infra-red-cut Films to Hide itself from LiDAR
Yuki Fukatsu, Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU)
pp. 190 - 195
HWS2023-96
Feasibility Study of Instrumentation Security for Infrastructure Monitoring Camera
Nagisa Nishimura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.)
pp. 196 - 197
HWS2023-97
Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography
Kosei Nakamura, Makoto Ikeda (UT)
pp. 198 - 203
HWS2023-98
Composable Security in High Level Synthesis for Cipher Circuit Implementation
Mingyu Yang, Gento Hiruma (Titech), Kazuo Sakiyama, Yang Li (UEC), Yuko Hara-Azumi (Titech)
pp. 204 - 208
HWS2023-99
eFPGA-based IP Protection of Embedded Processor Design
Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara (Tokyo Tech)
pp. 209 - 214
HWS2023-100
A Study on formal verification of GF(2^m) arithmetic circuits including states
Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.)
pp. 215 - 220
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.