Wed, Dec 2 AM  10:20 - 11:40
(1) ICD	10:20-10:40	A Circuit Design Method based on Foreknown Regularity between I/O CPM2009-134 ICD2009-63	Jin Sato, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.)
(2) ICD	10:40-11:00	Implementation of Asynchronous Bus for GALS System CPM2009-135 ICD2009-64	Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.)
(3) ICD	11:00-11:20	A WiMAX Turbo Decoder with Tailbiting BIP Architecture CPM2009-136 ICD2009-65	Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ.), Hisanori Fujisawa (Fujitsu Laboratories Ltd.), Takashi Ito (Tohoku Univ.)
(4) ICD	11:20-11:40	A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise CPM2009-137 ICD2009-66	Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST)
Wed, Dec 2 PM  13:15 - 17:00
(5)	13:15-13:50	[Invited Talk] PI/SI/EMI for Chip/Package/Board Co-Design CPM2009-138 ICD2009-67	Hideki Asai (Shizuoka Univ.)
(6)	13:50-14:25	[Invited Talk] Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices -- Impacts and Hardening Techniques down to 22nm Design Rule -- CPM2009-139 ICD2009-68	Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.)
(7)	14:25-15:00	[Invited Talk] Noise characteristics improvement of an LSI by using an interposer embedded capacitors CPM2009-140 ICD2009-69	Yoshiyuki Saito, Eiji Takahashi, Chie Sasaki (Panasonic), Yasuhiro Sugaya (Panasonic Electronic Devices)
	15:00-15:15	Break ( 15 min. )
(8)	15:15-15:50	[Invited Talk] EMC jisso Design at GHz frequencies CPM2009-141 ICD2009-70	Takashi Harada, Naoki Kobayashi, Ken Morishita, Hisashi Ishida (NEC Corp.)
	15:50-16:00	Break ( 10 min. )
(9)	16:00-17:00	[Panel Discussion] EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side -- CPM2009-142 ICD2009-71	Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan)
Wed, Dec 2 PM  13:25 - 15:05
(10)	13:25-13:45
(11)	13:45-14:05
(12) VLD	14:05-14:25	Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis VLD2009-43 DC2009-30	Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST)
(13) VLD	14:25-14:45	A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System VLD2009-44 DC2009-31	Kazuhito Ito, HyunJoon Kim (Saitama Univ.)
(14) VLD	14:45-15:05	A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI VLD2009-45 DC2009-32	Hidekazu Seto, Kazuhito Ito (Saitama Univ.)
	15:05-15:20	Break ( 15 min. )
Wed, Dec 2 PM  15:20 - 16:40
(15) VLD	15:20-15:40	Evaluation of Hardware/Software Partitioning Method with Consideration of Timing VLD2009-46 DC2009-33	Junya Matsunaga, Michiaki Muraoka (Kochi Univ.)
(16) VLD	15:40-16:00	Two-level Cache Simulation with L2 Unified Cache for Embedded Applications VLD2009-47 DC2009-34	Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(17) VLD	16:00-16:20	Simulation-Based Bus Width Optimization for Two-Level Cache VLD2009-48 DC2009-35	Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
(18)	16:20-16:40
Thu, Dec 3 AM  10:00 - 11:35
(19) CPM	10:00-10:20	Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data CPM2009-143 ICD2009-72	Kenichi Shimbo, Tadanobu Toba, Hidehumi Ibe, Koji Nishii (Hitachi)
(20) CPM	10:20-10:40	A Target Imedance of Power Distribution Network and LSI Packaging Design CPM2009-144 ICD2009-73	Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC)
(21) CPM	10:40-11:00	Evaluation of Waveform-Improvement performance on the Segmental Transmission Line CPM2009-145 ICD2009-74	Yuki Shimauchi, Hiroshi Nakayama, Yoshiki Yamaguchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.)
(22)	11:00-11:35	[Invited Talk] Study on the Signal Integrity Design of a High-Speed LSI and a Printed Circuit Board CPM2009-146 ICD2009-75	Seiichi Saito, Keitaro Yamagishi (Mitsubishi Electric)
Thu, Dec 3 AM  10:00 - 11:40
(23) VLD	10:00-10:20	An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits VLD2009-49 DC2009-36	Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
(24) DC	10:20-10:40	BILBO register with Soft Error Detection Function VLD2009-50 DC2009-37	Masahiro Sugasawa, Kazuteru Namba, Hideo Ito (Chiba Univ.)
(25) DC	10:40-11:00	An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism VLD2009-51 DC2009-38	Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo)
(26) DC	11:00-11:20	A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures VLD2009-52 DC2009-39	Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ)
(27)	11:20-11:40
Thu, Dec 3 AM  10:20 - 11:40
(28) CPSY	10:20-10:40	An Efficient GPU Implementation Approach of Smith-Waterman Algorithm CPSY2009-43	Keisuke Dohi (Nagasaki Univ.), Ling Cheng (Univ of Edinburgh), Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.), Khaled Benkrid (Univ of Edinburgh)
(29) CPSY	10:40-11:00	Improvement and evaluation of mode switching approach for Variable Level Cache CPSY2009-44	Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)
(30) CPSY	11:00-11:20	Fine-grain Mode Transition Controller based on Dynamic Memory Access Analyzing for Variable Stages Pipeline CPSY2009-45	Kazumasa Nomura, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)
(31) CPSY	11:20-11:40	Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method CPSY2009-46	Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
Thu, Dec 3 PM  13:25 - 14:25
(32) DC	13:25-13:45	Detection of Fault Candidate portions by DEF data Visualization VLD2009-53 DC2009-40	Kazuaki Kishi, Masaru Sanada (Kochi Univ. of Tech.)
(33) DC	13:45-14:05	A Yield Model with Testability and Repairability VLD2009-54 DC2009-41	Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(34) DC	14:05-14:25	Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity VLD2009-55 DC2009-42	Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST)
	14:25-15:20	Break ( 55 min. )
Thu, Dec 3 PM  15:20 - 16:20
(35) VLD	15:20-15:40	Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array VLD2009-56 DC2009-43	Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
(36) VLD	15:40-16:00	A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter VLD2009-57 DC2009-44	Kimio Shibata, Cong-Kha Pham (Univ. of Electro-Comm.)
(37)	16:00-16:20
Thu, Dec 3 PM  13:25 - 15:05
(38) RECONF	13:25-13:45	A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration RECONF2009-41	Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(39) RECONF	13:45-14:05	An inversion/non-inversion dynamic optical reconfiguration architecture using a MEMS RECONF2009-42	Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
(40) RECONF	14:05-14:25	Optical buffering technique under space radiation environment RECONF2009-43	Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
(41) RECONF	14:25-14:45	Evaluation of circuit proliferation method that uses concept of pressure in PCA RECONF2009-44	Yuta Araki, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.)
(42) RECONF	14:45-15:05	Protocol for Expansion of Hardware in a Scalable FPGA System	Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT)
	15:05-15:20	Break ( 15 min. )
Thu, Dec 3 PM  15:20 - 16:20
(43) RECONF	15:20-15:40	A Virus Scanning Engine Using a Parallel Sieve Method and the MPU RECONF2009-45	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.)
(44) RECONF	15:40-16:00	Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures RECONF2009-46	Toshihiro Katashita (AIST), Yohei Hori (Chuo Univ.), Akashi Satoh (AIST)
(45) RECONF	16:00-16:20	Evaluation of CryptMT steam cipher implemented on FPGA RECONF2009-47	Naoko Yamada (Keio Univ.), Atsunori Sakurai, Keisuke Iwai, Takakazu Kurokawa (National Defense Academy), Hideharu Amano (Keio Univ.)
Thu, Dec 3 PM  16:30 - 18:00
(46)	16:30-18:00
Fri, Dec 4 AM  10:00 - 11:40
(47) VLD	10:00-10:20	A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk VLD2009-58 DC2009-45	Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.)
(48) VLD	10:20-10:40	Increasing Yield Using Partially-Programmable Circuits VLD2009-59 DC2009-46	Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
(49) VLD	10:40-11:00	Transistor-Array-Based Opamp Layout and its Evaluationon VLD2009-60 DC2009-47	Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu)
(50) VLD	11:00-11:20	Analysis of Layout Structure Dependence on Distance/Space Variation for MOS Transistors VLD2009-61 DC2009-48	Yuichi Sadohira, Shigetoshi Nakatake (Univ. of Kitakyusyu)
(51)	11:20-11:40
Fri, Dec 4 AM  10:20 - 11:40
(52) CPSY	10:20-10:40	Precise Detection of Stack-Smashing Attacks and Requirements for its Efficient Implement CPSY2009-47	Shohei Noma, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama (Kyoto Inst. of Tech.)
(53) CPSY	10:40-11:00	A Proposal of Message Driven IP Core Interface CPSY2009-48	Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.)
(54) CPSY	11:00-11:20	A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation -- On the Instruction Control Unit -- CPSY2009-49	Yuta Totsuka, Masamichi Makino, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.)
(55) CPSY	11:20-11:40	A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation -- On the Memory Management Unit -- CPSY2009-50	Masamichi Makino, Yuta Totsuka, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.)
Fri, Dec 4 AM  10:00 - 11:00
(56) RECONF	10:00-10:20	"FLOPS2D" Design Concept -- Floating Point Custom Computer for CFD -- RECONF2009-48	Naoyuki Fujita (JAXA)
(57) RECONF	10:20-10:40	A Study of two input LUT array type programmable logic architecture for cryptographic processing RECONF2009-49	Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.)
(58) RECONF	10:40-11:00	Selection Technique of Pipeline Parameters for FLOPS-2D:Multi-FPGA System Environment RECONF2009-50	Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
Fri, Dec 4 PM  13:25 - 14:45
(59) DC	13:25-13:45	A Test Compaction Oriented Don't Care Identification Method VLD2009-62 DC2009-49	Motohiro Wakazono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
(60) DC	13:45-14:05	A secure design for testability of RSA Encryption circuits VLD2009-63 DC2009-50	Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
(61) DC	14:05-14:25	Logic stabilization way of open fault with unsuitable logic -- Aim in simple diagnosis technology -- VLD2009-64 DC2009-51	Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.)
(62) DC	14:25-14:45	A Path Selection Method of Delay Test for Transistor Aging VLD2009-65 DC2009-52	Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST)
	14:45-15:00	Break ( 15 min. )
Fri, Dec 4 PM  15:00 - 16:20
(63) VLD	15:00-15:20	Evaluation of Energy Consumption on Multipliers Using the Sum of Operands VLD2009-66 DC2009-53	Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.)
(64) VLD	15:20-15:40	Automatic Generation of Design-Specific Cell Libraries VLD2009-67 DC2009-54	Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
(65) VLD	15:40-16:00	FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs VLD2009-68 DC2009-55	Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
(66)	16:00-16:20
Fri, Dec 4 PM  13:25 - 14:25
(67) RECONF	13:25-14:25	[Invited Talk] A Project on Dynamically Reconfigurable Processors: MuCCRA -- Design emvironment, Low Power design and 3D wireless interconnect -- RECONF2009-51	Hideharu Amano (Keio Univ.)
	14:25-15:00	Break ( 35 min. )
Fri, Dec 4 PM  15:00 - 16:00
(68) RECONF	15:00-15:20	An Optimal Algorithm for 3-adress QDD Machine Code RECONF2009-52	Taisuke Fukuyama, Tsutomu Sasao, Munehiro Matsuura (Kyusyu Inst. of Tech.)
(69) RECONF	15:20-15:40	Performance Evaluation of Dynamially Reconfigurable VLD Circuit	Kiyotaka Komoku, Takashi Miyake, Takayuki Morishita (Okayama Pref. Univ.)
(70) RECONF	15:40-16:00	Implementation of core functions of a H264 encoder on STP-engine RECONF2009-53	Yoshihiro Takamatsu, Takao Toi, Hideharu Amano (Keio Univ.)

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
	Contact Address	Nozomu Togawa (Waseda Univ.) E-: n Tel: +81-3-5286-3908, Fax: +81-3-3208-7439
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
CPM	Technical Committee on Component Parts and Materials (CPM)   [Latest Schedule]
	Contact Address
ICD	Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
	Contact Address	Minoru Fujishima (The University of Tokyo) TEL 03-5841-7425,FAX 03-5841-8575 E-:eetu-
CPSY	Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
	Contact Address	Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-: am-u
DC	Technical Committee on Dependable Computing (DC)   [Latest Schedule]
	Contact Address	Masato Kitakami Graduate School of Advanced Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +43.290.3039 E-:fultyba-u
RECONF	Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
	Contact Address	Nobuya WATANABE (Okayama Univ.) E-: bu-u TEL: +81-86-251-8251 FAX: +81-86-251-8251
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
	Contact Address

Last modified: 2009-11-26 12:08:32